2:1, Differential-to-3.3V Dual LVPECL/ECL
Clock Multiplexer
ICS85356I
DATA SHEET
General Description
The ICS85356I is a dual 2:1 Differential-to-LVPECL
Multiplexer. The device has both common select and
HiPerClockS™
individual select inputs. When COM_SEL is logic High,
the CLKxx input pairs will be passed to the output.
When COM_SEL is logic Low, the output is
determined by the setting of the SEL0 pin for channel 0 and the
SEL1 pin for Channel 1.
Features
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High speed differential muliplexer. The device can be configured
as a 2:1 multiplexer
Dual 3.3V LVPECL outputs
Selectable differential CLKx/nCLKx input pairs
Differential CLKx/nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency: 900MHz (typical)
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx input
Output skew: 75ps (typical)
Propagation delay: 1.15ns (typical)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type to
LVPECL. It can also be used in ECL mode by setting V
CC
= 0V and
V
EE
to -3.0V to - 3.8V.
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
Block Diagram
CLK0A
Pulldown
nCLK0A
Pullup
Pin Assignment
Q0
nQ0
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
0
CLK0B
Pulldown
CLK0B
Pullup
1
SEL0
Pullup
COM_SEL
Pulldown
SEL1
Pullup
CLK1A
Pulldown
nCLK1A
Pullup
CLK1B
Pulldown
CLK1B
Pullup
ICS85356I
0
Q1
nQ1
1
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
ICS85356I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
ICS85356AMI REVISION B MAY 10, 2010
1
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
14, 20
1
2
3, 8
4
5
6
7
9
10
11
12, 13
15, 17
16
18, 19
Name
V
CC
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
CLK1B
nCLK1B
V
EE
nQ1,Q1
SEL1, SEL0
COM_SEL
nQ0,Q0
Power
Input
Input
Unused
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Output
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Type
Description
Positive supply pins.
Non-inverting differential clock input.
Inverting differential clock input.
No connect.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Clock select inputs. LVCMOS/LVTTL interface levels.
Common select input. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3. Control Input Function Table
Inputs
COM_SEL
0
0
0
0
1
SEL1
0
0
1
1
x
SEL0
0
1
0
1
x
Q0
CLK0A
CLK0B
CLK0A
CLK0B
CLK0B
nQ0
nCLK0A
nCLK0B
nCLK0A
nCLK0B
nCLK0B
Outputs
Q1
CLK1A
CLK1A
CLK1B
CLK1B
CLK1B
nQ1
nCLK1A
nCLK1A
nCLK1B
nCLK1B
nCLK1B
ICS85356AMI REVISION B MAY 10, 2010
2
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
20 Lead SOIC
20 Lead TSSOP
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
73.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±0.3V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
40
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V±0.3V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
SEL0, SEL1
COM_SEL
SEL0, SEL1
COM_SEL
V
CC
= V
IN
= 3.6V
V
CC
= V
IN
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µ
µA
µ
I
IL
ICS85356AMI REVISION B MAY 10, 2010
3
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Table 4C. Differential DC Characteristics,
V
CC
= 3.3V±0.3V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
CLK0A, CLK0B,
CLK1A, CLK1B
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
CLK0A, CLK0B,
CLK1A, CLK1B
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
Test Conditions
V
CC
= V
IN
= 3.6V
V
CC
= V
IN
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.0
V
CC
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IH
Input
High Current
I
IL
Input
Low Current
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Range; NOTE 1, 2
NOTE 1: VIL should not be less than -0.3V
NOTE 2: Common mode voltage is defined as V
IH
.
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V±0.3V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50Ω to V
CC
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V±0.3V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(o)
t
R
/ t
F
t
ODC
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle Skew
20% to 80%
200
ƒ
≤
900MHz
0.85
Test Conditions
Minimum
Typical
900
1.15
75
1.45
150
580
100
Maximum
Units
MHz
ns
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions
NOTE: All parameters measured at ƒ
≤
622MHz, unless otherwise noted.
NOTE: This part does not add measurable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
ICS85356AMI REVISION B MAY 10, 2010
4
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Parameter Measurement Information
2V
VCC
V
CC
Qx
SCOPE
nCLKxA,
nCLKxB
V
PP
Cross Points
V
CMR
LVPECL
nQx
V
EE
CLKxA,
CLKxB
VEE
-1.3V ± 0.3V
LVPECL Output Load AC Test Circuit
Differential Input Level
nQx
nQx
nQy
nQy
nQ0, nQ1
80%
80%
V
SW I N G
Q0, Q1
20%
t
R
t
F
20%
tsk(o)
Output Skew
Output Rise/Fall Time
nCLKxA,
nCLKxB
nCLKxA,
nCLKxB
CLKxA,
CLKxB
nQ0, nQ1
Q0, Q1
CLKxA,
CLKxB
nQ0, nQ1
Q0, Q1
t
PD
tp
LH
tp
HL
tsk(odc) =
tp
LH
- tp
HL
Propagation Delay
Output Duty Cycle Skew
ICS85356AMI REVISION B MAY 10, 2010
5
©2010 Integrated Device Technology, Inc.
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