72210L10TPG datasheet, PDF - EEWORLD Datasheet

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72210L10TPG: DescriptionPDIP-28, Tube; Categorystorage storage; File Size222KB，12 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72210L10TPG Overview

PDIP-28, Tube

72210L10TPG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	PDIP
package instruction	DIP-28
Contacts	28
Manufacturer packaging code	PTG28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	6.5 ns
Maximum clock frequency (fCLK)	100 MHz
period time	10 ns
JESD-30 code	R-PDIP-T28
JESD-609 code	e3
length	34.67 mm
memory density	4096 bit
Memory IC Type	OTHER FIFO
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	28
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512X8
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.005 A
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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CMOS SyncFIFO™

64 x 8, 256 x 8,

512 x 8, 1,024 x 8,

2,048 x 8 and 4,096 x 8

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

IDT72420

IDT72200

IDT72210

IDT72220

IDT72230

IDT72240

FEATURES:

•

64 x 8-bit organization (IDT72420)

256 x 8-bit organization (IDT72200)

512 x 8-bit organization (IDT72210)

1,024 x 8-bit organization (IDT72220)

2,048 x 8-bit organization (IDT72230)

4,096 x 8-bit organization (IDT72240)

10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/

72240)

Read and Write Clocks can be asynchronous or coincidental

Dual-Ported zero fall-through time architecture

Empty and Full flags signal FIFO status

Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,

respectively

Output enable puts output data bus in high-impedance state

Produced with advanced submicron CMOS technology

Available in 28-pin 300 mil plastic DIP

For surface mount product please see the IDT72421/72201/72211/

72221/72231/72241 data sheet

Green parts available, see ordering information

DESCRIPTION:

The IDT72420/72200/72210/72220/72230/72240 SyncFIFO™ are very

high-speed, low-power First-In, First-Out (FIFO) memories with clocked read

and write controls. These devices have a 64, 256, 512, 1,024, 2,048, and 4,096

x 8-bit memory array, respectively. These FIFOs are applicable for a wide

variety of data buffering needs, such as graphics, Local Area Networks (LANs),

and interprocessor communication.

These FIFOs have 8-bit input and output ports. The input port is controlled

by a free-running clock (WCLK), and a Write Enable pin (WEN). Data is written

into the Synchronous FIFO on every clock when

WEN

is asserted. The output

port is controlled by another clock pin (RCLK) and a Read Enable pin (REN).

The Read Clock can be tied to the Write Clock for single clock operation or the

two clocks can run asynchronous of one another for dual clock operation. An

Output Enable pin (OE) is provided on the read port for three-state control of

the output.

These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full

(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided

for improved system control. The partial (AE) flags are set to Empty+7 and Full-

7 for

and

respectively.

These FIFOs are fabricated using high-speed submicron CMOS technol-

ogy.

FUNCTIONAL BLOCK DIAGRAM

D0 - D7

WCLK

WEN

INPUT REGISTER

FLAG

LOGIC

RAM ARRAY

64 x 8, 256 x 8,

512 x 8, 1,024 x 8,

2,048 x 8, 4,096 x 8

WRITE CONTROL

LOGIC

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

Q0 - Q7

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

REN

2680 drw01

COMMERCIAL TEMPERATURE RANGE

FEBRUARY 2018

DSC-2680/7

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