3D7438
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
Super-Fine Resolution
(SERIES 3D7438)
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Leading- and trailing-edge accuracy
Programmable via serial or parallel interface
Increment range:
50ps through 250ps
Delay tolerance:
0.5% (See Table 1)
Supply current:
3mA typical
Temperature stability:
1.5%
max (-40C to 85C)
Vdd stability:
0.5%
max (4.75V to 5.25V)
PACKAGES
IN
SO
AE
GND
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
SI
1
2
3
4
8
7
6
5
VDD
OUT
SC
SI
3D7438Z-xx SOIC8
IN
AE
P0
P1
P2
P3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
OUT
P7
P6
P5
P4
GND
3D7438S-xx SOW16
3D7438D-xx SOIC14
For mechanical dimensions, click
here.
For package marking details, click
here.
FUNCTIONAL DESCRIPTION
The 3D7438 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
T
i,nom
= T
inh
+ i * T
inc
where i is the programmed address, T
inc
is the delay increment (equal
to the device dash number), and T
inh
is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
OUT
MD
AE
P0-P7
SC
SI
SO
VDD
GND
Signal Input
Signal Output
Mode Select
Address Enable
Parallel Data Input
Serial Clock
Serial Data Input
Serial Data Output
+5 Volts
Ground
The all-CMOS 3D7438 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard surface mount 16-pin SOL. An 8-pin SOIC
package is available for applications where the parallel interface is not needed. Similarly, a 14-pin SOIC is
offered for applications where the serial interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7438x-50
3D7438x-60
3D7438x-75
3D7438x-80
3D7438x-100
3D7438x-125
3D7438x-150
3D7438x-200
3D7438x-250
DELAYS AND TOLERANCES
Inherent
Delay (ns)
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
7.0
0.5
Delay
Range (ns)
12.750
.05
15.300
.06
19.125
.08
20.400
.08
25.500
.10
31.875
.13
38.250
.15
51.000
.20
63.750
.25
Delay
Step (ps)
50
25
60
30
75
38
80
40
100
50
125
63
150
75
200
100
250
125
Max Freq
(Addr=0)
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
INPUT RESTRICTIONS
Max Freq
(Addr=255)
98 MHz
82 MHz
65 MHz
61 MHz
49 MHz
39 MHz
32 MHz
24 MHz
19 MHz
Min P.Width
(Addr=0)
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
Min P.Width
(Addr=255)
5.1 ns
6.1 ns
7.6 ns
8.1 ns
10.0 ns
12.7 ns
15.3 ns
20.4 ns
25.5 ns
NOTES: Replace the ‘x’ in the part number with D, S or Z, depending on choice of package.
Any dash number between 50 and 250 not shown is also available as standard.
See application notes section for more details
2010
Data Delay Devices
Doc #10004
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7438
APPLICATION NOTES
GENERAL INFORMATION
The 8-bit programmable 3D7438 delay line
architecture is comprised of a sequence of five
identical delay cells connected in series, all of
which are controlled by a common current. This
current, in turn, is controlled by the user-selected
programming data (the address). The delay cells
produce at their output a replica of the signal
present at the input, shifted in time. The change
in delay from one address setting to the next is
called the
increment,
or LSB. It is nominally equal
to the device dash number. The minimum delay,
achieved by setting the address to zero, is called
the
inherent delay.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
where T
inh
is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 1.0 ns,
whichever is greater, at every address.
The
inherent delay error
is the deviation of the
inherent delay from its nominal value. For all
dash numbers, it is limited to 0.5 ns.
DELAY STABILITY
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D7438 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
The 3D7438 is designed to be most stable at the
maximum address setting (255). At this operating
condition, the thermal coefficient of the absolute
delay is limited to
250
PPM/C, which is
equivalent to a variation, over the -40C to 85C
operating range, of
1.5%
from the room-
temperature delay. At smaller address settings
the thermal coefficient will be somewhat larger.
At the maximum address, the power supply
sensitivity of the absolute delay is
0.5%
over the
4.75V to 5.25V operating range, with respect to
the delay at the nominal 5.0V power supply. At
smaller address settings the sensitivity will be
somewhat larger.
DELAY ACCURACY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the
differential nonlinearity
(DNL), also referred
to as the increment error. It is defined as the
deviation of the increment at a given address
from its nominal value. For all dash numbers, the
DNL is within 0.5 LSB at every address (see
Table 1: Delay Step).
The
integrated nonlinearity
(INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The
relative error
is defined as follows:
e
rel
= (T
i
– T
0
) – i * T
inc
where i is the address, T
i
is the measured delay
at the i’th address, T
0
is the measured inherent
delay, and T
inc
is the nominal increment. It is very
similar to the INL, but simpler to calculate. For all
dash numbers, the relative error is less than 1.0
LSB at every address (see Table 1: Delay
Range).
The
absolute error
is defined as follows:
e
abs
= T
i
– (T
inh
+ i * T
inc
)
INPUT SIGNAL CHARACTERISTICS
The maximum input frequency and minimum
input pulse width are both limited by the device.
Exceeding either limit will cause the signal to be
blocked by the line. Furthermore, for a given
device, these limitations vary with the user-
specified address. The relationships are:
F
Max
= 1250 / (i * T
inc
)
PW
Min
= 0.4 * (i * T
inc
),
where F
Max
is in MHz, and PW
Min
& T
inc
are in ns.
These relationships break down for small delays:
F
Max
can never be greater than 150 MHz, and
PW
Min
can never be smaller than 3.3 ns.
PROGRAMMING INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D7438 delay program interface. Since the
3D7438 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VDD or Ground.
Doc #10004
7/8/2010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7438
APPLICATION NOTES (CONT’D)
TRANSPARENT PARALLEL MODE
(MD = 1, AE = 1)
The eight program pins P0 - P7 directly control
the output delay. A change on one or more of
the program pins will be reflected on the output
delay after a time
t
PDV
, as shown in Figure 2. A
register is required if the programming data is
bused.
LATCHED PARALLEL MODE
(MD = 1, AE PULSED)
The eight program pins P0 - P7 are loaded by the
falling edge of the Enable pulse, as shown in
Figure 3. After each change in delay value, a
settling time
t
EDV
is required before the input is
accurately delayed.
SERIAL MODE (MD = 0)
While observing data setup (t
DSC
) and data hold
(t
DHC
) requirements, timing data is loaded in
MSB-to-LSB order by the rising edge of the clock
(SC) while the enable (AE) is high, as shown in
Figure 4. The falling edge of the enable (AE)
activates the new delay value which is reflected
at the output after a settling time
t
EDV
. As data is
shifted into the serial data input (SI), the previous
contents of the 8-bit input register are shifted out
of the serial output port pin (SO) in MSB-to-LSB
order, thus allowing cascading of multiple
devices by connecting the serial output pin (SO)
of the preceding device to the serial data input
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in a
cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time
t
EQV
, bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
The SO pin, if unused, must be allowed to float if
the device is configured in the serial
programming mode.
The serial mode is the
only
mode available on
the 8-pin version of the 3D7438, and this mode is
unavailable
on the 14-pin version of the 3D7438.
SIGNAL IN IN
PROGRAMMABLE
DELAY LINE
OUT SIGNAL OUT
ADDRESS ENABLE AE
SERIAL INPUT SI
SHIFT CLOCK
SC
LATCH
SO
SERIAL OUTPUT
8-BIT INPUT
REGISTER
MODE SELECT MD
P0
P1
P2
P3
P4
P5
P6
P7
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS
NEW VALUE
t
PDX
PREVIOUS
t
PDV
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
Doc #10004
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7438
APPLICATION NOTES (CONT’D)
t
EW
ENABLE
(AE)
t
DSE
PARALLEL
INPUTS
P0-P7
DELAY
TIME
NEW VALUE
t
DHE
t
EDX
PREVIOUS
t
EDV
NEW VALUE
Figure 3: Latched parallel mode (MD=1)
t
EW
ENABLE
(AE)
t
ES
CLOCK
(SC)
t
CW
t
CW
t
EH
t
DSC
SERIAL
INPUT
(SI)
SERIAL
OUTPUT
(SO)
DELAY
TIME
NEW
BIT 7
t
DHC
NEW
BIT 6
NEW
BIT 0
t
EGV
OLD
BIT 7
t
CQV
OLD
BIT 6
t
CQX
OLD
BIT 0
t
EQZ
t
EDV
NEW
VALUE
t
EDX
PREVIOUS VALUE
Figure 4: Serial mode (MD=0)
3D7438
SI
SO
AE
3D7438
SI
SC
SO
AE
3D7438
SI
SC
SO
AE
FROM
WRITING
DEVICE
SC
TO
NEXT
DEVICE
Figure 5: Cascading Multiple Devices
TABLE 2: DELAY VS. PROGRAMMED ADDRESS
PARALLEL
SERIAL
STEP 0
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 253
STEP 254
STEP 255
CHANGE
P7
Msb
PROGRAMMED ADDRESS
P6
P5
P4
P3
P2
P1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
P0
Lsb
NOMINAL DELAY (NS)
PER 3D7438 DASH NUMBER
-50
7.000
7.050
7.100
7.150
7.200
7.250
19.650
19.700
19.750
12.750
-75
7.000
7.075
7.150
7.225
7.300
7.375
25.975
26.050
26.125
19.125
-100
7.000
7.100
7.200
7.300
7.400
7.500
32.300
32.400
32.500
25.500
-125
7.000
7.125
7.250
7.375
7.500
7.625
38.625
38.750
38.875
31.875
-150
7.000
7.150
7.300
7.450
7.600
7.750
44.950
45.100
45.250
38.250
-200
7.000
7.200
7.400
7.600
7.800
8.000
57.600
57.800
58.000
51.000
-250
7.000
7.250
7.500
7.750
8.000
8.250
70.250
70.500
70.750
63.750
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
1
Doc #10004
7/8/2010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
3D7438
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
0.8
1.0
1.0
-4.0
TYP
3.0
MAX
5.0
UNITS
mA
V
V
A
A
mA
mA
2.5
ns
NOTES
Addr = 128
-35.0
4.0
15.0
2.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Clock Frequency
Enable Width
Clock Width
Data Setup to Clock
Data Hold from Clock
Data Setup to Enable
Data Hold from Enable
Enable to Serial Output Valid
Enable to Serial Output High-Z
Clock to Serial Output Valid
Clock to Serial Output Invalid
Enable Setup to Clock
Enable Hold from Clock
Parallel Input Valid to Delay Valid
Parallel Input Change to Delay Invalid
Enable to Delay Valid
Enable to Delay Invalid
Input Pulse Width
Input Period
Input to Output Delay
SYMBOL
f
C
t
EW
t
CW
t
DSC
t
DHC
t
DSE
t
DHE
t
EQV
t
EQZ
t
CQV
t
CQX
t
ES
t
EH
t
PDV
t
PDX
t
EDV
t
EDX
t
WI
Period
t
PLH
, t
PHL
MIN
10
10
10
3
10
3
20
20
20
10
10
10
20
0
35
0
40
80
45
40
TYP
MAX
80
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
% of Delay
% of Delay
ns
NOTES
See Table 1
See Table 1
See Table 2
Doc #10004
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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