PI6C20800S
PCI Express® 1:8
HCSL Clock Buffer
Features
• Phase jitter filter for PCIe
®
application
• Eight Pairs of Differential Clocks
• Low skew < 50ps (PI6C20800S), <60ps (PI6C20800SI)
• Low Cycle-to-cycle jitter < 70ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Industrial Temperature Option - PI6C20800SI
• Packaging (Pb-Free & Green):
— 48-Pin SSOP (V)
— 48-Pin TSSOP (A)
Description
PI6C20800S is a PCI Express
®
, high-speed, low-noise differential
clock buffer designed to be a companion to PI6C410BS PCI
Express clock generator for Intel server chipsets. The device
distributes the differential SRC clock from PI6C410BS to eight
differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is
LOW. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is LOW, the output
clocks are Tristated. When PWRDWN# is LOW, the SDA and
SCLK inputs must be Tristated.
Block Diagram
Pin Configuration
SRC_DIV#
V
DD
V
SS
SRC
SRC#
OE_0
OE_3
OUT0
OUT0#
VSS
V
DD
OUT1
OUT1#
OE_1
OE_2
OUT2
OUT2#
V
SS
V
DD
OUT3
OUT3#
PLL/BYPASS#
SCLK
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE_INV
OE [0:7]
SRC_STOP#
PWRDWN#
SCLK
SDA
PLL/BYPASS#
SRC_DIV#
SRC
SRC#
Output
Control
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
DIV
OUT6
OUT6#
OUT7
OUT7#
LOCK
SMBus
Controller
PLL_BW#
PLL
V
DD_A
V
SS_A
I
REF
LOCK
OE_7
OE_4
OUT7
OUT7#
OE_INV
V
DD
OUT6
OUT6#
OE_6
OE_5
OUT5
OUT5#
V
SS
V
DD
OUT4
OUT4#
PLL_BW#
SRC_STOP#
PWRDWN#
V
SS
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03/27/13
PCI Express® 1:8 HCSL Clock Buffer
Pin Descriptions
Pin
Name
SRC_DIV#
SRC & SRC#
OE [0:7]
Type
Input
Input
Input
Pin #
1
4, 5
6, 7, 14, 15, 35, 36,
43, 44
40
Descriptions
3.3V LVTTL input for selecting input frequency divide by 2,
active LOW.
0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active HIGH.
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
PI6C20800S
OE_INV
Input
OUT[0:7] & OUT[0:7]#
PLL/BYPASS#
SCLK
SDA
I
REF
SRC_STOP#
PLL_BW#
PWRDWN#
LOCK
V
DD
V
SS
V
SS_A
V
DD_A
Output
Input
Input
I/O
Input
Input
Input
Input
Output
Power
Ground
Ground
Power
8, 9, 12, 13, 16 17,
20, 21, 29, 30, 33, 34, 0.7V Differential outputs
37, 38, 41, 42
22
23
24
46
27
28
26
45
2, 11, 19, 31, 39
3, 10, 18, 25, 32
47
48
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active LOW
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active LOW
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
W/R
0/1
Data Write Protocol
(1)
1 bit
Start
bit
7 bits
Slave
Addr
1
W
1
Ack
8 bits
1
8 bits
Byte
Count
= N
1
Ack
8 bits
Data
Byte
Offset
1
Ack
8 bits
Data
Byte N
- 1
1
Ack
1 bit
Stop bit
Register
Ack
offset
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PCI Express® 1:8 HCSL Clock Buffer
Data Read Protocol
(2)
1 bit
Start
bit
7 bits
Slave
Addr
1
W
1
Ack
8 bits
Register
offset
1
Ack
1
Repeat
Start
7 bits
Slave
Addr
1
R
1
Ack
8 bits
Byte
Count
= N
1
Ack
8 bits
Data
Byte
Offset
1
Ack
8 bits
Data
Byte
N - 1
1
Not
Ack
1 bit
Stop
bit
PI6C20800S
Note:
2. Register offset for indicating the starting register for indexed block write and indexed block read.
Data Byte 0: Control Register
Bit
0
Descriptions
SRC_DIV#
0 = Divide by 2
1 = Normal
PLL/BYPASS#
0 = Fanout
1 = PLL
PLL Bandwidth
0 = HIGH Bandwidth,
1 = LOW Bandwidth
RESERVED
RESERVED
RESERVED
SRC_STOP#
0 = Driven when stopped
1 = Tristate
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
Type
RW
Power Up Condition
1 = x1
Output(s) Affected
OUT[0:7], OUT[0:7]#
Pin
NA
1
RW
1 = PLL
OUT[0:7], OUT[0:7]#
NA
2
3
4
5
6
RW
1 = Low
OUT[0:7], OUT[0:7]#
NA
7
RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
NA
Data Byte 1: Control Register
Bit
0
1
2
3
4
5
6
7
OUTPUTS enable
1 = Enabled
0 = Disabled
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
Pin
NA
NA
NA
NA
NA
NA
NA
NA
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PCI Express® 1:8 HCSL Clock Buffer
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
7
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
Output(s) Affected
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
Pin
NA
NA
NA
NA
NA
NA
NA
NA
PI6C20800S
Data Byte 3: Control Register
Bit
0
1
2
3
4
5
6
7
RESERVED
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
Output(s) Affected
Pin
Data Byte 4: Pericom ID Register
Bit
0
1
2
3
4
5
6
7
Pericom ID
Descriptions
Type
R
R
R
R
R
R
R
R
Power Up Condition
0
0
0
0
0
1
0
0
Output(s) Affected
NA
NA
NA
NA
NA
NA
NA
NA
Pin
NA
NA
NA
NA
NA
NA
NA
NA
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PCI Express® 1:8 HCSL Clock Buffer
Functionality
PWRDWN#
1
0
OUT
Normal
I
REF
× 2 or Float
OUT#
Normal
LOW
SRC_Stop#
1
0
OUT
Normal
I
REF
× 6 or Float
OUT#
Normal
LOW
PI6C20800S
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
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