BX80525U800256E datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> BX80525U800256E

BX80525U800256E: DescriptionMicroprocessor, 32-Bit, 800MHz, CMOS,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size879KB，102 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

BX80525U800256E Overview

Microprocessor, 32-Bit, 800MHz, CMOS,

BX80525U800256E Parametric

Parameter Name	Attribute value
Maker	Intel
package instruction	,
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	800 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	R-XXMA-X
low power mode	YES
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
speed	800 MHz
Nominal supply voltage	1.65 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	UNSPECIFIED
Terminal location	UNSPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

Preview

Download Datasheet

View All

Pentium

III Processor for the SC242 at

450 MHz to 800 MHz

Datasheet

Product Features

Available in 800EB, 733, 667, 600B,

600EB, 533B, and 533EB MHz speeds

support a 133 MHz system bus (‘B’ denotes

support for a 133 MHz system bus; ‘E’

denotes support for Advanced Transfer

Cache and Advanced System Buffering)

Available in 800, 750, 700, 650, 600E, 600,

550E, 550, 500, and 450 MHz speeds

support a 100 MHz system bus (‘E’ denotes

support for Advanced Transfer Cache and

Advanced System Buffering)

Available in versions that incorporate

256 KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC)) or versions that

incorporate a discrete, half-speed, 512 KB

in-package L2 cache with ECC

Dual Independent Bus (DIB) architecture

increases bandwidth and performance over

single-bus processors

Internet Streaming SIMD Extensions for

enhanced video, sound and 3D

performance

Binary compatible with applications

running on previous members of the Intel

microprocessor line

Dynamic execution micro architecture

Power Management capabilities

— System Management mode

— Multiple low-power states

Intel Processor Serial Number

Optimized for 32-bit applications running

on advanced 32-bit operating systems

Single Edge Contact Cartridge (S.E.C.C.)

and S.E.C.C.2 packaging technology; the

S.E.C. cartridges deliver high performance

with improved handling protection and

socketability

Integrated high performance 16 KB

instruction and 16 KB data, nonblocking,

level one cache

Enables systems which are scaleable up to

two processors

Error-correcting code for System Bus data

The Pentium

III

processor is designed for high-performance desktops and for workstations and

servers. It is binary compatible with previous Intel Architecture processors. The Pentium

III

processor provides great performance for applications running on advanced operating systems

such as Windows* 98, Windows NT and UNIX*. This is achieved by integrating the best

attributes of Intel processors—the dynamic execution, Dual Independent Bus architecture plus

Intel MMX™ technology and Internet Streaming SIMD Extensions—bringing a new level of

performance for systems buyers. The Pentium

III

processor is scaleable to two processors in a

multiprocessor system and extends the power of the Pentium II processor with performance

headroom for business media, communication and internet capabilities. Systems based on

Pentium

III

processors also include the latest features to simplify system management and lower

the cost of ownership for large and small business environments. The Pentium

III

processor

offers great performance for today’s and tomorrow’s applications.

December 1999

Order Number:

244452-005

Pentium

III Processor for the SC242 at 450 MHz to 800 MHz

Contents

1.0

Introduction......................................................................................................................... 9

1.1

Terminology.........................................................................................................10

1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10

1.1.2 Processor Naming Convention...............................................................11

Related Documents.............................................................................................11

Processor System Bus and V

REF .......................................................................................... 13

Clock Control and Low Power States..................................................................14

2.2.1 Normal State—State 1 ...........................................................................15

2.2.2 AutoHALT Powerdown State—State 2...................................................15

2.2.3 Stop-Grant State—State 3 .....................................................................15

2.2.4 HALT/Grant Snoop State—State 4 ........................................................16

2.2.5 Sleep State—State 5..............................................................................16

2.2.6 Deep Sleep State—State 6 ....................................................................16

2.2.7 Clock Control..........................................................................................17

Power and Ground Pins ......................................................................................17

Decoupling Guidelines ........................................................................................17

2.4.1 Processor VCC

CORE

Decoupling............................................................17

2.4.2 Processor System Bus AGTL+ Decoupling............................................18

Processor System Bus Clock and Processor Clocking .......................................18

Voltage Identification ...........................................................................................18

Processor System Bus Unused Pins...................................................................20

Processor System Bus Signal Groups ................................................................20

2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................21

2.8.2 System Bus Frequency Select Signal (BSEL0)......................................21

Test Access Port (TAP) Connection....................................................................23

Maximum Ratings................................................................................................24

Processor DC Specifications...............................................................................25

AGTL+ System Bus Specifications .....................................................................29

System Bus AC Specifications ............................................................................30

BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and

Measurement Guidelines ....................................................................................38

AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and

Measurement Guidelines ....................................................................................39

3.2.1 Overshoot/Undershoot Magnitude .........................................................39

3.2.2 Overshoot/Undershoot Pulse Duration...................................................40

3.2.3 Overshoot/Undershoot Activity Factor....................................................40

3.2.4 Reading Overshoot/Undershoot Specification Tables............................41

3.2.5 Determining if a System meets the Overshoot/Undershoot

Specifications .........................................................................................42

AGTL+ and Non-AGTL+ Ringback Specifications and Measurement

Guidelines ...........................................................................................................44

3.3.1 Settling Limit Guideline...........................................................................46

1.2

2.0

2.1

2.2

Electrical Specifications....................................................................................................13

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3.0

3.1

3.2

Signal Quality Specifications ............................................................................................38

3.3

Datasheet

Pentium

III Processor for the SC242 at 450 MHz to 800 MHz

4.0

Thermal Specifications and Design Considerations......................................................... 47

4.1

Thermal Specifications........................................................................................ 48

4.1.1 Thermal Diode........................................................................................ 50

S.E.C.C. Mechanical Specifications.................................................................... 51

S.E.C.C.2 Mechanical Specification.................................................................... 58

S.E.C.C.2 Structural Mechanical Specification ................................................... 64

Processor Package Materials Information .......................................................... 66

Intel

Pentium

III Processor Signal Listing........................................................ 66

Intel

Pentium

III Processor Core Pad to Substrate Via Assignments .............. 75

5.6.1 Processor Core Pad Via Assignments (CPUID 067xh).......................... 75

5.6.2 Processor Core Signal Assignments (CPUID 067xh) ............................ 75

5.6.3 Processor Core Pad Via Assignments (CPUID 068xh).......................... 88

Introduction ......................................................................................................... 89

Fan Heatsink Mechanical Specifications............................................................. 89

6.2.1 Boxed Processor Fan Heatsink Dimensions .......................................... 89

6.2.2 Boxed Processor Fan Heatsink Weight.................................................. 91

6.2.3 Boxed Processor Retention Mechanism ................................................ 91

Fan Heatsink Electrical Requirements ................................................................ 92

6.3.1 Fan Heatsink Power Supply ................................................................... 92

Fan Heatsink Thermal Specifications.................................................................. 93

6.4.1 Boxed Processor Cooling Requirements ............................................... 93

Alphabetical Signals Reference .......................................................................... 94

Signal Summaries ............................................................................................. 101

5.0

S.E.C.C. and S.E.C.C.2 Mechanical Specifications......................................................... 51

5.1

5.2

5.3

5.4

5.5

5.6

6.0

Boxed Processor Specifications....................................................................................... 89

6.1

6.2

6.3

6.4

7.0

Intel

Pentium

III Processor Signal Description ............................................................. 94

7.1

7.2

Datasheet

Pentium

III Processor for the SC242 at 450 MHz to 800 MHz

Figures

Second Level (L2) Cache Implementation ........................................................... 7

AGTL+ Bus Topology ..........................................................................................12

Stop Clock State Machine ...................................................................................12

BSEL[1:0] Example for a 100 MHz System Design

(100 MHz Processor Installed) ............................................................................20

BSEL[1:0] Example for a 100/133 MHz Capable System

(100 MHz Processor Installed) ............................................................................21

BSEL[1:0] Example for a 100/133 MHz Capable System

(133 MHz Processor Installed) ............................................................................21

BCLK, PICCLK, and TCK Generic Clock Waveform...........................................33

System Bus Valid Delay Timings ........................................................................33

System Bus Setup and Hold Timings..................................................................34

System Bus Reset and Configuration Timings....................................................34

Power-On Reset and Configuration Timings.......................................................34

Test Timings (TAP Connection) ..........................................................................35

Test Reset Timings .............................................................................................35

BCLK and PICCLK Generic Clock Waveform .....................................................36

Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot

Waveform ............................................................................................................42

Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................44

Signal Overshoot/Undershoot, Settling Limit, and Ringback 1............................44

S.E.C.Cartridge — 3-Dimensional View..............................................................45

S.E.C.Cartridge 2 — Substrate View ..................................................................46

Processor Functional Die Layout (CPUID 068xh) ...............................................47

S.E.C.C. Packaged Processor — Multiple Views................................................49

S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions ....50

S.E.C.C. Packaged Processor — Bottom View Dimensions...............................50

S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,

and Cover Lug Dimensions .................................................................................51

S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,

and Cover Detail Dimensions (Reference Dimensions Only)..............................52

S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment

Detail Dimensions ...............................................................................................53

S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment

Detail Dimensions, Continued .............................................................................54

S.E.C.C. Packaged Processor Substrate — Edge Finger Contact

Dimensions..........................................................................................................54

S.E.C.C. Packaged Processor Substrate — Edge Finger Contact

Dimensions, Detail A ...........................................................................................55

Intel

Pentium

III Processor Markings (S.E.C.C. Packaged Processor) ...........55

S.E.C.C.2 Packaged Processor — Multiple Views..............................................56

S.E.C.C.2 Packaged Processor Assembly — Primary View...............................57

S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......57

S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section ...58

S.E.C.C.2 Packaged Processor Assembly — Side View ....................................58

Detail View of Cover in the Vicinity of the Substrate Attach Features.................58

S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact

Dimensions..........................................................................................................59

S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact

Dimensions (Detail A)..........................................................................................59

Datasheet

Recommended Resources

A soft starter drives the control circuit of three electric motors b

Bipolar regulated power supply circuit using SW1468 voltage regulator block 3

AC voltmeter circuit composed of milliammeter b

Dual timing multiplexer circuit

Bingfeng brand BY-135A refrigerator circuit

Square wave generator with variable pulse width

Serial port opening method problem under WINCE: In VC, you can open the serial port like this: CreateFile("COM1",....), but in EVC, why do you have to do this: CreateFile(_T("COM1:"),....)? My question is: why do you need a semicolon after COM1? It...; 33love Embedded System

changeDisplaySetting rotates the screen, and the video playback is distorted?: In Windows Mobile 6.5, the display driver uses DDraw. If ChangeDisplaySettingEx is called to rotate the screen while a video is playing, the video will be distorted, but other applications are fine. W...; jlt2007 Embedded System

Electronic password lock based on single chip microcomputer: Can anyone help me with this program?...; 欣欣已上线 MCU

When I first learned ModelSimSE, I was confused about some concepts for a few days: eeworldpostqq...; blink FPGA/CPLD

wince-GDI test (waiting online): I put the GDIAPI TEST \WINCE500\PRIVATE\TEST\GWES\GDI\GDIAPI on PB, and the compilation error is as follows: BUILD: [01:0000000110:PROGC ] Linking obj\ARMV4Ietail\GDIAPItest.dll BUILD: [01:0000000129:...; guochenfang Embedded System

Driver loading in Windows Mobile: I'm porting the BSP of wince6.0 to windows mobile 6. I use kitl to trace the startup process. It's like this: filesys.exe loads nanflash driver, device.exe loads device manager. The device manager als...; markov Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components