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7007L15JG

Description
PLCC-68, Tube
Categorystorage    storage   
File Size485KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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7007L15JG Overview

PLCC-68, Tube

7007L15JG Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePLCC
package instructionQCCJ, PGA68,11X11
Contacts68
Manufacturer packaging codePLG68
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionPLCC
Maximum access time15 ns
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee3
length24.2062 mm
memory density262144 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.005 A
Minimum standby current4.5 V
Maximum slew rate0.285 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2062 mm
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Features
7007L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 68-pin PLCC and a 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
14L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
14R
A
0R
(1,2)
Address
Decoder
15
MEMORY
ARRAY
15
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
M/S
SEM
R
INT
R
(2)
2940 drw 01
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
SEPTEMBER 2019
1
DSC 2940/16
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