MT5C1001EC-45L/883C datasheet, PDF

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MT5C1001EC-45L/883C: DescriptionStandard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, LCC-32; Categorystorage storage; File Size135KB，13 Pages; ManufacturerMicross; Websitehttps://www.micross.com

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MT5C1001EC-45L/883C Overview

Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, LCC-32

MT5C1001EC-45L/883C Parametric

Parameter Name	Attribute value
Maker	Micross
Parts packaging code	DLCC
package instruction	SON,
Contacts	32
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	45 ns
JESD-30 code	R-CDSO-N32
length	20.955 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	1
Number of functions	1
Number of terminals	32
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1MX1
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Filter level	MIL-STD-883 Class C
Maximum seat height	2.54 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm

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Austin Semiconductor, Inc.

1M x 1 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY

SPECIFICATIONS

• SMD 5962-92316

• MIL-STD-883

MT5C1001

Limited Availability

PIN ASSIGNMENT

(Top View)

SRAM

28-Pin DIP (C)

(400 MIL)

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

WE\

Vss

Vcc

CE\

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

WE\

Vss

Vcc

CE\

FEATURES

•

High Speed: 20, 25, 35, and 45

Battery Backup: 2V data retention

Low power standby

Single +5V (+10%) Power Supply

Easy memory expansion with CE\ and OE\ options.

All inputs and outputs are TTL compatible

Three-state output

32-Pin Flat Pack (F)

OPTIONS

• Timing

20ns access

25ns access

35ns access

45ns access

55ns access

70ns access

• Package(s)

Ceramic DIP (400 mil)

Ceramic LCC

Ceramic Flatpack

Ceramic SOJ

MARKING

-20

-25

-35

-45

-55*

-70*

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

WE\

Vss

Vcc

CE\

DCJ

No. 109

No. 207

No. 303

No. 501

GENERAL DESCRIPTION

The MT5C1001 employs low power, high-performance

silicon-gate CMOS technology. Static design eliminates the

need for external clocks or timing strobes while CMOS circuitry

reduces power consumption and provides for greater

reliability.

For flexibility in high-speed memory applications, ASI

offers chip enable (CE\) and output enable (OE\) capability.

These enhancements can place the outputs in High-Z for addi-

tional flexibility in system design. Writing to these devices is

accomplished when write enable (WE|) and CE\ inputs are both

LOW. Reading is accomplished when WE\ remains HIGH while

CE\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled. This allows system designs to

achieve low standby power requirements.

The “L” version provides an approximate 50 percent

reduction in CMOS standby current (I

SBC2

) over the standard

version.

All devices operation from a single +5V power supply

and all inputs and outputs are fully TTL compatible.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

• Operating Temperature Ranges

Industrial (-40

C to +85

Military (-55 C to +125 C)

• 2V data retention/low power

*Electrical characteristics identical to those provided for the

45ns access devices.

For more products and information

please visit our web site at

www.austinsemiconductor.com

MT5C1001

Rev. 2.0 2/00

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