MOSEL VITELIC
V53C318160A
3.3 VOLT 1M X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Fast Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
50
50 ns
25 ns
35 ns
90 ns
60
60 ns
30 ns
40 ns
104 ns
70
70 ns
35 ns
45 ns
124 ns
Features
s
1M x 16-bit organization
s
Fast Page Mode for a sustained data rate
of 29 MHz
s
RAS access time: 50, 60, 70 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh, and
Self Refresh.
s
Refresh Interval: 1024 cycles/16 ms
1024 cycles/256 ms (L-version)
s
Available in 42-pin 400 mil SOJ and 50/44-pin
400 mil TSOP-II
s
Single +3.3 V
±0.3
V Power Supply
s
LVTTL Interface
Description
The V53C318160A is a 1048576 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C318160A offers Fast Page mode op-
eration. The V53C318160A has an symmetric
address, 10-bit row and 10-bit column.
All inputs are LVTTL compatible. Fast Page
Mode operation allows random access up to 1024 x
16 bits, within a page, with cycle times as short as
35 ns.
These features make the V53C318160A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
K
•
Access Time (ns)
50
•
Power
70
•
T
•
60
•
Std.
•
L
•
Temperature
Mark
Blank
V53C318160A Rev. 1.4 March 1998
1
MOSEL VITELIC
42-Pin Plastic SOJ
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
I/O
5
I/O
6
I/O
7
I/O
8
NC
NC
WE
RAS
NC
NC
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
311816500-02
V53C318160A
50/44-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
I/O
5
I/O
6
I/O
7
I/O
8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
NC
NC
WE
RAS
NC
NC
A
0
A
1
A
2
A
3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
311816500-03
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
A
0
–A
9
RAS
UCAS
LCAS
WE
OE
I/O
1
–I/O
16
V
CC
V
SS
NC
Row, Column Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Input, Output
+3.3V Supply
0V Supply
No Connect
Description
SOJ
TSOP-II
Pkg.
K
T
Pin Count
42
50
V53C318160A Rev. 1.4 March 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
°C
Storage temperature range ............... -55 to 150
°C
Soldering temperature ..................................260
°C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (V
CC
+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
V53C318160A
Capacitance*
T
A
= 25
°C,
V
CC
= 3.3 V
±
0.3 V, V
SS
= 0 V, f = 1 MHz
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS, UCAS, LCAS,
WE, OE
Data Input/Output
Min.
—
—
—
Max.
5
7
7
Unit
pF
pF
pF
*
Note:
Capacitance is sampled and not 100% tested.
Block Diagram
1024 x 16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
DATA I/O BUS
COLUMN DECODERS
Y0–Y9
I/O 1
I/O2
I/O3
I/O4
I/O 5
I/O6
I/O7
SENSE AMPLIFIERS
REFRESH
COUNTER
1024 x 16
10
A0
A1
I/O
BUFFER
I/O8
I/O 9
I/O10
I/O11
ADDRESS BUFFERS
AND PREDECODERS
ROW
DECODERS
X0– X9
1024
I/O12
•
•
•
A8
A9
MEMORY
ARRAY
1024 x 1024 x 16
I/O 13
I/O14
I/O15
I/O16
3118165A-04
V53C318160A Rev. 1.4 March 1998
3
MOSEL VITELIC
DC and Operating Characteristics
(1-2)
T
A
= 0
°C
to 70
°C,
V
CC
= 3.3 V
±
0.3 V, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Access
Time
V53C318160A
Min.
–10
V53C318160A
Symbol
I
LI
I
LO
I
CC1
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
V
CC
Supply Current,
Operating
Typ.
Max.
10
Unit
mA
mA
mA
Test Conditions
V
SS
£
V
IN
£
V
CC
+ 0.3V
V
SS
£
V
OUT
£
V
CC
+ 0.3V
RAS, CAS at V
IH
t
RC
= t
RC
(min.)
Notes
1
–10
10
1
50
60
70
200
180
160
2
2, 3, 4
I
CC2
I
CC3
V
CC
Supply Current,
TTL Standby
V
CC
Supply Current,
RAS-Only Refresh
50
60
70
mA
RAS, CAS at V
IH
other inputs
³
V
SS
t
RC
= t
RC
(min.)
2, 4
200
180
160
55
50
45
1.0
mA
I
CC4
V
CC
Supply Current,
Fast Page Mode
Operation
50
60
70
mA
Minimum Cycle
2, 3, 4
I
CC5
I
CC6
V
CC
Supply Current,
CMOS Standby
Average Self Refresh Current
CBR cycle with t
RAS
> t
RASS
min.,
CAS held low, WE = V
CC
– 0.2V,
Address and D
IN
= V
CC
– 0.2V
or 0.2V
V
CC
Supply Current,
during CAS-before-RAS Refresh
50
60
70
mA
RAS
³
V
CC
– 0.2 V,
CAS
³
V
CC
– 0.2 V
L version
1
1.0
250
mA
mA
I
CC7
200
180
160
–0.5
2
0.8
V
CC
+0.5
0.4
2.4
mA
t
RC
= t
RC
(min)
2, 4
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
I
OL
= 2 mA
I
OH
= –2 mA
1
1
1
1
V53C318160A Rev. 1.4 March 1998
4
MOSEL VITELIC
AC Characteristics
T
A
= 0
°C
to 70
°C,
V
CC
= 3.3 V
±0.3
V, V
SS
= 0V, t
T
= 2ns unless otherwise noted
JEDEC
Symbol Symbol
t
RL1RH1
t
RL2RL2
t
RH2RL2
t
RL1CH1
t
CL1CH1
t
RL1CL1
t
WH2CL2
t
AVRL2
t
RL1AX
t
AVCL2
t
CL1AX
t
RAS
t
RC
t
RP
t
CSH
t
CAS
t
RCD
t
RCS
t
ASR
t
RAH
t
ASC
t
CAH
V53C318160A
50
Parameter
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time
CAS to RAS Precharge Time
Read Command Hold Time
Referenced to CAS
Read Command Hold Time
Referenced to RAS
Output Hold after CAS LOW
Access Time from OE
Access Time from CAS
Access Time from RAS
Access Time from Column Address
CAS to Low-Z Output
Output Buffer Turnoff Delay
Data to CAS Low Delay
RAS to Column Address Delay Time
Output Buffer Turnoff Delay from OE
Write Command to CAS Lead Time
Write Command Setup Time
Write Command Hold Time
Write Pulse Width
Data to OE Delay
Write Command to RAS Lead Time
Data in Setup Time
0
0
0
13
0
13
0
8
8
0
13
0
25
13
13
60
70
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Min. Max. Min. Max. Min. Max. Unit Notes
50
90
30
50
13
18
0
0
8
0
10
13
5
0
10K
37
10K
60
110
40
60
15
20
0
0
10
0
15
15
5
0
10K
45
10K
70
130
50
70
20
20
0
0
10
0
15
20
5
0
10K
50
10K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
t
CL1RH1(R)
t
RSH
t
CH2RL2
t
CH2WX
t
RH2WX
t
CL1
t
GL1QV
t
CL1QV
t
RL1QV
t
AVQV
t
CL1QX
t
CH2QX
t
CL1QZ
t
RL1AV
t
GL2QZ
t
WL1CH1
t
WL1CL2
t
CL1WH1
t
WL1WH1
t
GL1QZ
t
WL1RH1
t
DVWL2
t
CRP
t
RCH
t
RRH
t
COH
t
OAC
t
CAC
t
RAC
t
CAA
t
CLZ
t
OFF
t
DZC
t
RAD
t
OEZ
t
CWL
t
WCS
t
WCH
t
WP
t
DEO
t
RWL
t
DS
15
0
0
0
ns
9
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
13
13
50
25
5
15
15
60
30
0
0
0
15
0
15
0
10
10
0
15
0
30
15
15
5
20
20
70
35
0
0
0
15
0
20
0
10
10
0
17
0
35
17
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
15
11
8
15
7, 12
7, 12
7, 13
7
V53C318160A Rev. 1.4 March 1998
5
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