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PI6C48543LE

Description
3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer
Categorylogic    logic   
File Size357KB,7 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Environmental Compliance
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PI6C48543LE Overview

3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer

PI6C48543LE Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP20,.25
Contacts20
Reach Compliance Codecompli
ECCN codeEAR99
series6C
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su2.2 ns
propagation delay (tpd)2.2 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.04 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width4.4 mm
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Features
Maximum operation frequency: 800 MHz
4 pair of differential LVDS outputs
Selectable differential CLK and PCLK inputs
CLK,
n
CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL
and HCSL input level
PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
Output Skew: 40ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.2ns (maximum)
3.3V power supply
Pin-to-pin compatible to ICS8543
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green):
-20-pin TSSOP (L)
Description
The PI6C48543 is a high-performance low-skew LVDS fanout
buffer. PI6C48543 features two selectable differential inputs and
translates to four LVDS outputs. The inputs can also be configured
to single-ended with external resistor bias circuit. The CLK input
accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,
and PCLK input accepts LVPECL or SSTL or CML signals. The
outputs are synchronized with input clock during asynchronous
assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for
differential to LVDS translations and/or LVDS clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Block Diagram
Pin Diagram
D
Q
LE
GND
CLK_EN
CLK_SEL
CLK
n
CLK
CLK_EN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
0
n
Q
0
V
CC
Q
1
n
Q
1
CLK
n
CLK
PCLK
n
PCLK
0
1
Q
0
n
Q
0
Q
1
n
Q
1
Q
2
n
Q
2
Q
3
n
Q
3
PCLK
n
PCLK
Q
2
n
Q
2
OE
GND
V
CC
GND
Q
3
n
Q
3
CLK_SEL
OE
08-0247
1
PS8771B
10/02/08

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