PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Features
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Maximum operation frequency: 800 MHz
4 pair of differential LVDS outputs
Selectable differential CLK and PCLK inputs
CLK,
n
CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL
and HCSL input level
PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
Output Skew: 40ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.2ns (maximum)
3.3V power supply
Pin-to-pin compatible to ICS8543
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green):
-20-pin TSSOP (L)
Description
The PI6C48543 is a high-performance low-skew LVDS fanout
buffer. PI6C48543 features two selectable differential inputs and
translates to four LVDS outputs. The inputs can also be configured
to single-ended with external resistor bias circuit. The CLK input
accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,
and PCLK input accepts LVPECL or SSTL or CML signals. The
outputs are synchronized with input clock during asynchronous
assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for
differential to LVDS translations and/or LVDS clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Block Diagram
Pin Diagram
D
Q
LE
GND
CLK_EN
CLK_SEL
CLK
n
CLK
CLK_EN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
0
n
Q
0
V
CC
Q
1
n
Q
1
CLK
n
CLK
PCLK
n
PCLK
0
1
Q
0
n
Q
0
Q
1
n
Q
1
Q
2
n
Q
2
Q
3
n
Q
3
PCLK
n
PCLK
Q
2
n
Q
2
OE
GND
V
CC
GND
Q
3
n
Q
3
CLK_SEL
OE
08-0247
1
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Pin Description
Name
GND
CLK_EN
CLK_
SEL
CLK
n
CLK
Pin #
1, 9, 13
2
3
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
Type
P
I_PU
I_PD
I_PD
I_PU
I_PD
I_PU
I_PU
P
O
O
O
O
Connect to Ground
Description
Synchronized clock enable. When high, clock outputs follow clock input. When low, Q
x
outputs are forced low,
n
Q
x
outputs are forced high. LVCMOS/LVTTL level with 80kΩ pull up.
Clock select input. When high, selects CLK
1
input. When low, selects CLK
0
input. LVCMOS/
LVTTL level with 80kΩ pull down.
Non-inverting differential clock input
Inverting differential clock input
Non-inverting differential clock input
Inverting differential clock input
Output Enable, Controls outputs Q
0
,
n
Q
0
through Q
3
,
n
Q
3
Connect to 3.3V.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
PCLK
n
PCLK
OE
V
CC
Q
3
,
n
Q
3
Q
2
,
n
Q
2
Q
1
,
n
Q
1
Q
0
,
n
Q
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
C
IN
R_pullup
R_pulldown
Parameter
Input Capacitance
Input Pullup Resistance
Input Pulldown Resistance
Conditions
Min.
Typ.
6
80
80
Max.
Units
pF
kΩ
Control Input Function Table
Inputs
OE
1
1
1
1
0
Notes:
1.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
Outputs
Selected Source
CLK,
n
CLK
PCLK,
n
PCLK
CLK,
n
CLK
PCLK,
n
PCLK
Q
0
:Q
3
Diasbled: Low
Disabled: Low
Enabled
Enabled
Hi-Z
n
Q
0
:
n
Q
3
CLK_EN
0
0
1
1
x
CLK_SEL
0
1
0
1
x
Diasbled: High
Disabled: High
Enabled
Enabled
Hi-Z
08-0247
2
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
Enabled
nQ0:nQ3
Q0:Q3
Clock Input Function Table
(See Figure 2)
Inputs
CLK or PCLK
0
1
0
1
Biased; V
IN
=
Vcc/2
Biased; V
IN
=
V
CC
/2
n
CLK or
n
PCLK
Outputs
Q
0
:Q
3
LOW
HIGH
LOW
HIGH
HIGH
LOW
n
Q
0
:
n
Q
3
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
None Inverting
None Inverting
None Inverting
None Inverting
Inverting
Inverting
1
0
Biased; V
IN
= V
CC
/2
Biased; V
IN
= V
CC
/2
0
1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
STG
Parameter
Supply voltage
Input voltage
Output voltage
Storage temperature
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
Min.
Typ.
Max.
4.6
V
CC
+0.5V
V
CC
+0.5V
150
o
C
Units
V
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fi
cations only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
08-0247
3
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Operating Conditions
Symbol
V
CC
T
A
I
CC
Parameter
Power Supply Voltage
Ambient Temperature
Power Supply Current
Conditions
Min.
3.135
-40
Typ.
3.3
Max.
3.465
85
60
Units
V
o
C
mA
LVCMOS/LVTTL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
CLK_SEL
CLK_EN, OE
CLK_SEL
CLK_EN, OE
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
Conditions
Min.
2
-0.3
Typ.
Max.
3.765
0.8
150
5
μA
Units
V
Differential DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
I
IH
I
IL
V
PP
V
CMR
Input High
Current
Input Low
Current
Parameter
n
CLK,
n
PCLK
Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
Min.
Typ.
Max.
5
150
Units
uA
uA
uA
uA
CLK, PCLK
n
CLK,
n
PCLK
-150
-5
0.15
0.5
1.3
V
CC
-
0.85V
CLK, PCLK
Peak-to-peak Voltage
Common Mode Input Voltage
(1)
V
V
Notes:
1. For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+0.3V
LVPECL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
I
IH
I
IL
V
PP
V
CMR
Input High
Current
Input Low
Current
Parameter
n
CLK,
n
PCLK
Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
Min.
Typ.
Max.
5
150
Units
CLK, PCLK
n
CLK,
n
PCLK
-150
-5
0.3
1.5
1
V
CC
μA
CLK, PCLK
Peak-to-peak Voltage
Common Mode Input Voltage; Note
(1)
V
Notes:
1. For single ended applications, the maximum input voltage for PCLK and
n
PCLK is V
CC
+0.3V.
08-0247
4
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
LVDS DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
OZ
I
OFF
I
OSD
I
OS
V
OH
V
OL
Parameter
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
High Impedance Leakage Current
Power OFF Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
Output Voltage Low
0.9
-10
-20
±1
-3.5
-3.5
1.34
1.06
1.125
Conditions
Min.
200
Typ.
280
0
1.25
5
Max.
360
40
1.375
25
+10
+20
-5
-5
1.6
Units
mV
V
mV
μA
mA
V
AC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V)
Symbol
f
max
t
Pd
Tsk(o)
Tsk(pp)
t
r
/t
f
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output-to-output Skew
(2)
Part-to-part Skew
(3)
Output Rise/Fall time
Output duty cycle
20% - 80%
100
48
f
≤
800 MHz
1.0
Conditions
Min.
Typ.
Max.
800
2.2
40
300
300
52
%
ps
Units
MHz
ns
Notes:
1. Measured from the differenital input crossing point to the differential output crossing point
2 Skew between outputs with the same supply voltage and equal load conditions. Measured at the differential outputs crossing point.
3. Skew between outputs on different parts operating with the same supply voltage and equal load conditions. Measured at the differential out-
puts crossing point.
4. All parameters are measured at 500 MHz unless noted otherwise
Applications Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
08-0247
5
PS8771B
10/02/08
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