EBE10FE8ACFR-6E-E datasheet, PDF

Datasheet> All Categories > storage> storage> EBE10FE8ACFR-6E-E

EBE10FE8ACFR-6E-E: DescriptionDDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, FBDIMM-240; Categorystorage storage; File Size196KB，22 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en; Environmental Compliance

Download Datasheet Parametric View All

EBE10FE8ACFR-6E-E Overview

DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, FBDIMM-240

EBE10FE8ACFR-6E-E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ELPIDA
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	333 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,1.8 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.79 A
Maximum slew rate	2.02 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

EBE10FE8ACFR-6E-E Preview

DATA SHEET

1GB Fully Buffered DIMM

EBE10FE8ACFR

Specifications

•

Density: 1GB

•

Organization



128M words

72 bits, 1 rank

•

Mounting 9 pieces of 1G bits DDR2 SDRAM sealed

in FBGA

•

Package



240-pin fully buffered, socket type dual in line

memory module (FB-DIMM)

PCB height: 30.35mm

Lead pitch: 1.00mm



Advanced Memory Buffer (AMB): 655-ball FCBGA



Lead-free (RoHS compliant)

•

Power supply



DDR2 SDRAM: VDD

1.8V

0.1V



AMB: VCC

1.5V

0.075V/

−0.045V

•

Data rate: 667Mbps (max.)

•

Eight internal banks for concurrent operation

(components)

•

Interface: SSTL_18

•

Burst lengths (BL): 4, 8

•

/CAS Latency (CL): 3, 4, 5

•

Precharge: auto precharge option for each burst

access

•

Refresh: auto-refresh, self-refresh

•

Refresh cycles: 8192 cycles/64ms



Average refresh period

7.8µs at 0°C

≤

≤ +85°C

3.9µs at

+85°C <

≤ +95°C

•

Operating case temperature range



TC = 0°C to +95°C

Features

•

JEDEC standard Raw Card A Design

•

Industry Standard Advanced Memory Buffer (AMB)

•

High-speed differential point-to-point link interface at

1.5V (JEDEC spec)



14 north-bound (NB) high speed serial lanes



10 south-bound (SB) high speed serial lanes

•

Various features/modes:



MemBIST and IBIST test functions



Transparent mode and direct access mode for

DRAM testing



Interface for a thermal sensor and status indicator

•

Channel error detection and reporting

•

Automatic DDR2 SDRAM bus and channel

calibration

•

SPD (serial presence detect) with 1piece of 256 byte

serial EEPROM

Note: Warranty void if removed DIMM heat

spreader.

Performance

FB-DIMM

System clock

frequency

167MHz

Speed grade

PC2-5300F

Peak channel

throughput

8.0GByte/s

FB-DIMM link data rate

4.0Gbps

DDR2 SDRAM

Speed Grade

DDR2-667 (5-5-5)

DDR data rate

667Mbps

Document No. E1346E20 (Ver. 2.0)

Date Published October 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2008

EBE10FE8ACFR

Ordering Information

Part number

EBE10FE8ACFR-6E-E

DIMM speed

grade

PC2-5300F

Component JEDEC

speed bin (CL-tRCD-tRP)

DDR2-667 (5-5-5)

Mounted devices*

Mounted AMB*

IDT Rev. L4

EDE1108ACSE-8E-E

EDE1108ACSE-6E-E

Notes: 1. Please refer to the EDE1104ACSE, EDE1108ACSE, EDE1116ACSE datasheet (E0975E) for detailed

operation part and timing waveforms.

2. Please refer to the following documents for detailed operation part and timing waveforms.

Advanced Memory Buffer (AMB) specification

FB-DIMM Architecture and Protocol specification

Part Number

E B E 10 F E 8 A C F R - 6E - E

Elpida Memory

Type

B: Module

Environment code

E: Lead Free

(RoHS compliant)

Product Family

E: DDR2

DRAM Speed Grade

6E: DDR2-667 (5-5-5)

AMB Device Information

R: IDT, Rev.L4

Module Outline

F: 240-pin DIMM

Density / Rank

10: 1GB/1-rank

Module Type

F: Fully Buffered

Mono Density

E: 1Gbit

Mono Organization

8: x8

Die Rev. (Mono)

Power Supply, Interface

A: 1.8V, SSTL_1.8

Data Sheet E1346E20 (Ver. 2.0)

EBE10FE8ACFR

Advanced Memory Buffer Overview

The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol

Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large

memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing,

refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for

handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other

DIMMs on the FB-DIMM channel.

The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface.

FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is

288 devices per channel and total memory capacity scales with DRAM bit density.

The AMB is the buffer that isolates the DRAMs from the channel.

Advanced Memory Buffer Functionality

The AMB will perform the following FB-DIMM channel functions.

•

Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and

Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB

DIMM position.

•

Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or

DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames.

•

If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.

•

Detects errors on the channel and reports them to the host memory controller.

•

Support the FB-DIMM configuration register set as defined in the register chapters.

•

Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM.

•

Provides a read buffer FIFO and a write buffer FIFO.

•

Supports an SMBus protocol interface for access to the AMB configuration registers.

•

Provides logic to support MemBIST and IBIST design for test functions.

•

Provides a register interface for the thermal sensor and status indicator.

•

Functions as a repeater to extend the maximum length of FB-DIMM links.

Data Sheet E1346E20 (Ver. 2.0)

EBE10FE8ACFR

Advanced Memory Buffer Block Diagram

Southbound

10×2

Data in

10×2

Southbound

Data out

Reference

clock

1×2

PLL

Data merge

RE-time

Re-synch

Demux

PISO

/RESET

Reset

control

10×12

Thermal

sensor

failover

Command

decoder &

CRC check

Link init SM

and control

and CSRs

IBIST-RX

10×12

Init

patterns

Mux

IBIST-TX

DRAM clock

Command

out

DRAM

interface

Data out

DRAM

address and

command copy1

DRAM

address and

command copy2

DRAM

data and strobes

LAI logic

DRAM Command

Mux

DDR state controller

and CSRs

Core

controller

and CSRs

Write data

FIFO

External MemBIST

DDR calibration

Sync & idle

pattern

generator

IBIST-TX

IBIST-RX

Mux

72+18×2

Data in

Data CRC

generator and

Read FIFO

LAI

controller

NB LAI Buffer

Mux

Link init SM

and control

and CSRs

SMBus

controller

failover

14×6×2

PISO

14×12

Demux

Re-synch

RE-time

Data merge

Northbound 14×2

Data Out

14×2 Northbound

Data In

Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.

Data Sheet E1346E20 (Ver. 2.0)

EBE10FE8ACFR

Interfaces

Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,

one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or

an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on an FB-DIMM.

Memory Interface

NB FBD

out Link

SB FBD

in Link

AMB

NB FBD

in Link

SB FBD

out Link

SMB

Block Diagram AMB Interfaces

Interface Topology

The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8

DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven

to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the

next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the

direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives

the data to the next DIMM until the host is reached.

Host

Southbound

Nourthbound

AMB

n/c

Block Diagram FB-DIMM Channel Southbound and Northbound Paths

Data Sheet E1346E20 (Ver. 2.0)

Secondary or to

optional next FBD

Primary or Host

Direction

n/c

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

AVK200 home theater amplifier and maintenance 01

Hybrid power amplifier 02

Mark identification device circuit of automatic labeling machine

Rice cooker circuit drawing 21_hemisphere

HY1417PL F8 FM phase lock module circuit

Door lock alarm with time recognition function

How to realize automatic cycle charging and discharging of equipment based on WINCE system?: RT, do you have any good ideas? Thanks...; sdc666 Embedded System

Domestic oscilloscope ADC chip and domestic signal source DAC chip!: [color=#000]Domestic chips, everyone can learn about them! ADC:1. MXT2088 directly replaces AD9288 (100M) with dual 8-bit resolution. 2. MXT2002 directly replaces ADC08D500 (500M) with dual 8-bit reso...; qdk12 FPGA/CPLD

Motor drive development exchange 2: R&D process of motor drive products: Continue from the previous post: https://bbs.eeworld.com.cn/thread-1155638-1-1.htmlProduct development process:How does a product transform from market demand to prototype? See the following flowchart...; 安驱技术_孙大卫 Motor Drive Control（Motor Control）

Polarity of EPWMA pulse: I would like to ask: Why do the EPWMA and EPWMB pulses, which should have opposite polarities, appear to be one phase behind EPWMA and EPWMB?...; lzx_18570633112 Analog electronics

How can I reverse the PWM signal and then give it to the MOS tube?: [i=s]This post was last edited by wolfcan on 2016-9-21 20:57[/i] Hello experts, I am working on control algorithms, but I need to make a hardware circuit for experiments. Now I have a question for you...; wolfcan Power technology

485 Communication Problem: The 485 protocol format is generally used for large-scale communication of single-chip microcomputers. I checked the information of 485 IC 65HVN3082, which says "1/8 load--the bus can connect up to 25...; eeleader Industrial Control Electronics

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components