ISPLSI2064A-80LTN100 datasheet, PDF

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ISPLSI2064A-80LTN100: DescriptionEE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100; CategoryProgrammable logic devices Programmable logic; File Size417KB，14 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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ISPLSI2064A-80LTN100 Overview

EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100

ISPLSI2064A-80LTN100 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	LFQFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	compli
ECCN code	EAR99
Other features	YES
maximum clock frequency	57 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
JTAG BST	NO
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	64
Number of macro cells	64
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Programmable logic type	EE PLD
propagation delay	18.5 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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Lead-

Free

Package

Options

Available!

ispLSI 2064/A

In-System Programmable High Density PLD

Functional Block Diagram

Input Bus

Features

• ENHANCEMENTS

— ispLSI 2064A is Fully Form and Function Compatible

to the ispLSI 2064, with Identical Timing

Specifcations and Packaging

— ispLSI 2064A is Built on an Advanced 0.35 Micron

CMOS

Technology

Output Routing Pool (ORP)

Select devices have been discontinued.

See Ordering Information section for product status.

Output Routing Pool (ORP)

Input Bus

— 2000 PLD Gates

— 64 I/O Pins, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 125 MHz Maximum Operating Frequency

—

= 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

Input Bus

GLB

Logic

Array

D Q

0139Bisp/2064

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

The ispLSI 2064 and 2064A are High Density Program-

mable Logic Devices. The devices contain 64 Registers,

64 Universal I/O pins, four Dedicated Input pins, three

Dedicated Clock Input pins, two dedicated Global OE

input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The 2064 and 2064A feature 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 2064 and 2064A offer non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1…B7

(Figure 1). There are a total of 16 GLBs in the ispLSI 2064

and 2064A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Description

August 2006

2064_10

Input Bus

D Q

Output Routing Pool (ORP)

• HIGH DENSITY PROGRAMMABLE LOGIC

Global Routing Pool

(GRP)

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