STI728005D2-70VGT datasheet, PDF

STI728005D2-70VGT: DescriptionFast Page DRAM Module, 8MX72, 70ns, MOS, DIMM-168; Categorystorage storage; File Size322KB，8 Pages; ManufacturerSimple Tech Inc.

Download Datasheet Parametric View All

STI728005D2-70VGT Overview

Fast Page DRAM Module, 8MX72, 70ns, MOS, DIMM-168

Parameter Name	Attribute value
Maker	Simple Tech Inc.
package instruction	DIMM-168
Reach Compliance Code	unknown
access mode	FAST PAGE
Maximum access time	70 ns
Other features	RAS ONLY/CAS BEFORE RAS REFRESH
Spare memory width	36
JESD-30 code	R-XDMA-N168
memory density	603979776 bit
Memory IC Type	FAST PAGE DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
refresh cycle	2048
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	MOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	DUAL

C5000-How to BOOT a program larger than 48K: [size=3] For C5000, the method of BOOT for programs larger than 48K: For C5000, the on-chip BOOT program moves the contents of the data area to the RAM in the program area after power-on, so the FLASH...; Jacktang Microcontroller MCU

SEED-DIML138 board diagram help: I am using the SEED-DIML138 development board, but the core board and motherboard pictures in the CD do not match. For example, the pins corresponding to their DIM interfaces do not match. The motherb...; weibo1988821 DSP and ARM Processors

Problems encountered when learning FPGA: I want to make a driver for CT1628, and use three pins to serially output several sections of code. But the current program cannot be compiled, I don't know why. The program requires: COMMEND data can...; kingdom152479 FPGA/CPLD

Urgent, ActiveX control registration failed: I wrote an MFC smart control ActiveX control, and the generated name is MyControl.ocx. After using regsvr32 MyControl.ocx, it prompts: "MyControl.ocx" is not an executable file; there is no registrati...; yellowbo Embedded System

How to use pcie ip hard core: I want to make a data collection device. How to use the PCIe IP hard core? Should I modify the automatically generated example? Where should I modify it?...; qlc111 FPGA/CPLD

The Jilin Province Electronics Competition was delayed for half an hour, but it finally started...: [i=s]This post was last edited by paulhyde on 2014-9-15 08:54[/i] Everyone come and discuss!!...; pippin Electronics Design Contest

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components