Enhanced
Features
s
Memory Systems Inc.
DM1M64DT6/DM1M72DT6 Multibank EDO EDRAM
1Mb x 64/1Mb x 72 Enhanced DRAM DIMM
Product Specification
16Kbytes SRAM Cache Memory for 12ns Random Reads Within
Eight Active Pages (Multibank Cache)
s
Fast 8Mbyte DRAM Array for 30ns Access to Any New Page
s
Write Posting Registers for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
2Kbyte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Second
Cache Fill Rate
s
A Hit Pin Outputs Status on On-chip Page Hit/Miss Comparators to
Simplify Control
On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Coherency on Writes
s
Hidden Precharge & Refresh Cycles
s
Extended 64ms Refresh Period for Low Standby Power
s
CMOS/TTL Compatible I/O and +5 Volt Power Supply
s
Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
s
Description
The Enhanced Memory Systems 8MB enhanced DRAM
(EDRAM)DIMM module provides a single memory module solution
for the main memory or local memory of fast 64-bit embedded
computers, communications switches, and other high performance
systems. Due to its fast non-interleave architecture, the EDRAM DIMM
module supports zero-wait-state burst read or write operation to
83MHz. The EDRAM outperforms conventional SRAM plus DRAM or
synchronous DRAM memory systems by minimizing wait states on
initial reads (hit or miss) and eliminating writeback delays.
Each 8Mbyte DIMM module has 16Kbytes of SRAM cache
organized as eight 256 x 72 row registers with 12ns initial access
time. On a cache miss, the fast DRAM array reloads an entire 2Kbyte
row register over a 2Kbyte-wide bus in just 18ns for an effective cache
fill rate of 113.6 Gbytes/second. During write cycles, a write posting
register allows the initial write to be posted as early as 5ns after
column address is available. EDRAM supports direct non-interleave
page writes at up to 83MHz. An on-chip hit/miss comparator
automatically maintains cache coherency during writes.
Architecture
The DM1M72DT6 achieves
1Mb x 72 density by mounting 18
512Kx8 EDRAMs, packaged in low
profile 44-pin TSOP-II packages
on both sides of the multi-layer
substrate. Six high drive series
terminated buffer chips buffer
address and control lines.
Twenty-four surface mount
capacitors are used to decouple
the power supply bus. The
DM1M64DT6 contains 16 512Kx8
EDRAMs. The parity data components are not populated. The EDRAM
memory module architecture is very similar to two standard 4MB
DRAM SIMM modules configured in a 64-bit wide, non-interleave
configuration. The EDRAM module adds an integrated cache and
cache control logic which allow the cache to operate much like a
page mode or static column DRAM.
The EDRAM’s SRAM cache is
integrated into the DRAM array as tightly
coupled row registers. Memory reads
always occur from the 256 x 72 cache
row register associated with a 1MB
segment of DRAM. When the on-chip
comparator detects a page hit, only the
/QLE
SRAM is accessed and data is available
0,1
in 12ns from column address (the /HIT
/G
0,1
I/O
output is low to indicate a page hit).
Control
DQ
and
When a page miss is detected, the entire
0-71
Data
Latches
new DRAM row is loaded into cache and
/S
0,1
data is available at the output within
30ns from row enable (the /HIT output
/WE
0,1
is high to indicate a page miss).
Subsequent reads within a page (burst
reads or random reads) will continue at
V
12ns cycle time. Since reads occur from
C
the SRAM cache, the DRAM precharge
V
can occur simultaneously without
PD
CC
1-24
SS
Functional Diagram
CALA
0-8,
CALB
0-8
Column
Add
Latch
4-Bit
Comp
A
0-7
Column Decoder
8- 256 X 72 Cache Pages
(Row Register)
Sense Amps
& Column Write Select
A
0-10
4- Last
Row
Read
Add
Latches
Row Decoder
Row
Add
Latch
Memory
Array
(8 Mbyte + Parity)
/F
W/R
/RE
0,1
Row Add
and
Refresh
Control
A
0-9
Refresh
Counter
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2125-000
degrading performance. The on-chip refresh counter with
independent refresh bus allows the EDRAM to be refreshed during
cache reads.
Memory writes can be posted as early as 6.5ns after row
enable and are directed to the DRAM array. During a write hit, the
on-chip address comparator activates a parallel write path to the
SRAM cache to maintain coherency. Memory writes do not affect
the contents of the cache row register except during write hits.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior system performance at less cost, power, and
area than systems implemented with complex synchronous SRAM
cache, cache controllers, and multilevel data busses.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A
8
and A
9
. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
Functional Description
last row read address latch for the bank specified by row address
The EDRAM is designed to provide optimum memory
bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
performance with high speed microprocessors. As a result, it is
bank which is reloaded on each /RE active read miss cycle). If the
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write specified by the row and column address is available at the output
pins at the greater of times t
AC
or t
GQV
. The /HIT output is driven
operations even if data is written to another memory page. These
low at time t
HV
after /RE to indicate the shorter access time to the
capabilities, in conjunction with the faster basic DRAM and cache
external control logic. Since no DRAM activity is initiated, /RE can
speeds of the EDRAM, minimize processor wait states.
be brought high after time t
RE1
, and a shorter precharge time, t
RP1
,
Four Bank Cache Architecture (One of Two Banks)
HIT0
HIT1
HIT2
HIT3
Bank 3
Bank 2
Bank 1
Bank 0
/HIT
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-7
1M Array
1M Array
1M Array
1M Array
D
0-71
A
0-10
Data-In
Latch
256 x 72
Cache
Bank 0
CA
0-7
256 x 72
Cache
Bank 1
256 x 72
Cache
Bank 2
256 x 72
Cache
Bank 3
(0,0)
RA
8
, RA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
QLE
Data-Out
Latch
G
S
Q
0-71
2-164
is required. Additional locations within the currently active page
may be accessed concurrently with precharge by providing new
column addresses to the multiplex address inputs. New data is
available at the output at time t
AC
after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either t
AC
and t
CQV
.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times t
RAC
, t
AC
, and t
GQV
. The /HIT
output is driven high at time t
HV
after /RE to indicate the longer
access time to the external control logic. /RE may be brought high
after time t
RE
since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within the
currently active page may be accessed by providing new column
addresses to the multiplex address inputs. New data is available at
the output at time t
AC
after each column address change in static
column mode. During any read cycle, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid time
is determined by either t
AC
and t
CQV
.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
/RE Inactive Operation
address and data are posted to the DRAM as soon as the column
Data may be read from the SRAM cache without clocking /RE.
address is latched by bringing /CAL low and the write data is latched This capability allows the EDRAM to perform cache read
by bringing /WE low (both /CAL and /WE must be high when
operations during precharge and refresh cycles to minimize wait
initiating the write cycle with the falling edge of /RE). The write
states. It is only necessary to select /S and /G and provide the
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
address and data can be latched very quickly after the fall of /RE
(t
RAH
+ t
ASC
for the column address and t
DS
for the data). During a
write burst sequence, the second write data can be posted at time
t
RSW
after /RE. Subsequent writes within a page can occur with write
cycle time t
PC
. With /G enabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify, or random read-write
sequences within the page with 12ns cycle times. During a write hit
sequence, the /HIT output is driven low. At the end of any write
sequence (after /CAL and /WE are brought high and t
RE
is satisfied),
/RE can be brought high to precharge the memory. Cache reads can
be performed concurrently with precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for
the column address and t
DS
for the data). During a write burst
sequence, the second write data can be posted at time t
RSW
after
/RE. Subsequent writes within a page can occur with write cycle
time t
PC
. During a write miss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory. Cache
reads can be performed concurrently with the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads will
occur from the page accessed during the last /RE active read cycle.
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
Standby Current
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
2-165
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R, /G, and /F
Function
/S
/G
/CAL
A
0-7
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
Cache Read (Static Column)
L
L
H
Col Adr
operation. All combinations of addresses A
0-9
must be sequenced
Cache Read (Page Mode)
L
L
¤
Col Adr
every 64ms refresh period. A
10
does not need to be cycled. Read
refresh cycles are not allowed because a DRAM refresh cycle does
EDO Mode and Output Latch Enable Operation
not occur when a read refresh address matches the LRR address
The QLE and /CAL inputs can be used to create extended data
latch.
output (EDO) mode timings in either static column or page modes.
Low Power Mode
The DM1M72DT6 has an output latch enable (QLE) for each
The EDRAM enters its low power mode when /S is high. In this
logical bank that can be used to extend the data output valid time.
mode, the internal DRAM circuitry is powered down to reduce
The output latch enable operates as shown in the following table.
standby current.
When QLE is low, the latch is transparent and the EDRAM
operates identically to the standard EDRAMs. When /CAL is high
Initialization Cycles
during a static column mode read, the QLE input can be used to
A minimum of eight /RE active initialization cycles (read,
latch the output to extend the data output valid time. QLE can be
write, or refresh) are required before normal operation is
held high during page mode reads. In this case, the data outputs
guaranteed. Following these start-up cycles, two read cycles to
are latched while /CAL is high and open when /CAL is not high.
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A
8
and A
9
define the four internal DRAM banks.
QLE
/CAL
Comments
Unallowed Mode
L
X
Output Transparent
Read, write, or /RE only refresh operations must not be
¤
H
Output Latched When QLE=H (Static Column EDO)
performed to unselected memory banks by clocking /RE when /S is
high.
H
¤
Output Latched When /CAL=H (Page Mode EDO)
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
Write-Per-Bit Operation
optimize system performance, the interface to the EDRAM may be
The DM1M72 DIMM offers a write-per-bit capability to
simplified to reduce the number of control lines by either tying pins
selectively modify individual parity bits (DQ
8, 17, 26, 35, 44, 53, 62, 71
)
to ground or by tying one or more control inputs together. The QLE
for byte write operations. The parity devices (DM2213) are
inputs can be tied low if output latching is not required, or it can be
selected via /CALA
8
/CALB
8
. Byte write selection to non-parity bits is
tied high if “extended data out” (hyper page mode) is required. The
accomplished via /CALA
0-7
/CALB
0-7
. The bits to be written are
/HIT output pin is not necessary for device operation. The W/R and
determined by a bit mask data word which is placed on the parity
/G inputs can be tied together if reads are not required during a write
I/O data pins prior to clocking /RE. The logic one bits in the mask
hit cycle. The simplified control interface still allows the fast page
data select the bits to be written. As soon as the mask is latched by
read/write cycle times, fast random read/ write times, and hidden
/RE, the mask data is removed and write data can be placed on the
precharge functions available with the EDRAM.
data bus. The mask is only specified on the /RE transition. During
page mode burst write operations, the same mask is used for all
Pin Descriptions
write operations.
/RE
0-1
— Row Enable
ECC Operation
These inputs are used to initiate DRAM read and write
The DM1M72DT6-xxN supports error correction coding
operations and latch a row address. It is not necessary to clock /RE
(ECC) by replacing the parity chips with normal DM2203 devices.
to read data from the EDRAM SRAM row register. On read
This version does not support write-per-bit parity operation.
operations, /RE can be brought high as soon as data is loaded into
cache to allow early precharge.
2-166
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page and bank accessed during the last /RE active read cycle.
To perform a cache read in static column mode, /CAL is held high,
and the cache contents at the specified column address will be
valid at time t
AC
after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address. When /RE
is inactive, the hit pin is not driven and is in a high impedance
state.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit
cycles.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/CALA
0-8,
/CALB
0-8
— Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch contains the address present at the time
/CAL went low. Individual /CAL inputs are provided for each byte of
EDRAM to allow byte write capability.
W/R — Write/Read
This input along with /F input specifies the type of DRAM
operation initiated on the low going edge of /RE. When /F is high,
W/R specifies either a write (logic high) or read operation (logic
low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE
0,1
— Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both the /CAL for the
specified byte and /WE are low.
/G
0,1
— Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S
0,1
— Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in a powered-down condition.
Read or write cycles must not be executed when /S is high. /S must
remain low throughout any read or write operation. Only /F refresh
operation can be executed when, /S is not enabled.
DQ
0-71
— Data Input/Output
These CMOS/TTL bidirectional data pins are used to read and
write data to the EDRAM. On the DM2213 write-per-bit memory,
these pins are also used to specify the bit mask used during write
operations.
A
0-10
— Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
QLE
0,1
— Output Latch Enable
This input enables the EDRAM output latches. When QLE is
low, the output latch is transparent. Data is latched when both /CAL
and QLE are high. This allows output data to be extended during
either static column or page mode read cycles.
/HIT — Hit Pin
This output pin will be driven during /RE active read or write
cycles to indicate the hit/miss status of the cycle.
PD — Presence Detect
This output will indicate if the DIMM module is inserted in a
socket. When a DIMM is inserted, this pin is grounded. When no
DIMM is present, the pin is open.
V
CC
Power Supply
These inputs are connected to the +5 volt power supply.
V
SS
Ground
These inputs are connected to the power supply ground
connection.
2-167
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