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AS4DDR264M72PBG-3/IT

Description
DDR DRAM, 64MX72, 0.45ns, CMOS, PBGA255, 25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255
Categorystorage    storage   
File Size2MB,31 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

AS4DDR264M72PBG-3/IT Overview

DDR DRAM, 64MX72, 0.45ns, CMOS, PBGA255, 25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255

AS4DDR264M72PBG-3/IT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicross
Parts packaging codeBGA
package instruction25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255
Contacts255
Reach Compliance Codecompliant
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time0.45 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B255
JESD-609 codee0
length32 mm
memory density4831838208 bit
Memory IC TypeDDR DRAM
memory width72
Number of functions1
Number of ports1
Number of terminals255
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64MX72
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width25 mm
AS4DDR264M72PBG & MYXDDR264M72
iPEM
4.8 Gb SDRAM-DDR2
64Mx72 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Packages:
255 Plastic Ball Grid Array (PBGA), 25 x 32mm,
1.27mm pitch
208 PBGA, 16 x 22mm, 1.0mm pitch (page 27-28)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4n-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes (I/T Version)
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V
±0.1V
power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, 6 or 7
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5
Write latency = Read latency - 1* tCK
Organized as 64M x 72 w/ support for x80
Weight: AS4DDR264M72PBG ~ 3.5 grams typical
BENEFITS
Space conscious PBGA defined for easy
SMT manufacturability (1.27mm or
1.0mm pitch)
Reduced part count
Significant I/O reduction vs individual
CSP approach
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
64 Meg x 72
8 Meg x 16 x 8 Banks
8K
A0‐A12 (8k)
BA0‐BA2 (8)
A0‐A9 (1K)
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-1
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
2
2
2
3
3
A
VCCL
VSSDL
2
2
2
3
3
B
VCCL
VSSDL
2
2
2
3
3
C
VCCL
VSSDL
2
2
2
3
3
D
VCCL
VSSDL
DQ64-79
2
2
2
3
3
CS0\
CS1\
CS2\
CS3\
CS4\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
DQ0-15 B
DQ16-31 C
DQ32-47 D
DQ48-63
AS4DDR264M72PBG & MYXDDR264M72
Rev. 2.4 12/12
Micross Components reserves the right to change products or specifications without notice.
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