Numonyx
TM
StrataFlash
®
Embedded Memory
(P30-65nm)
256-Mbit, 512-Mbit (256M/256M)
Datasheet
Product Features
High performance
— 100 ns initial access for Easy BGA
— 110 ns initial access for TSOP
— 25 ns 16-word asynchronous-page read mode
— 52 MHz with zero WAIT states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16-, and continuous-word options for
burst mode
— Buffered Enhanced Factory Programming
(BEFP) at 2.0 MByte/s (Typ) using 512-word
buffer
— 1.8 V buffered programming at 1.5MByte/s
(Typ) using 512-word buffer
Security
— One-Time Programmable Register:
• 64 unique factory device identifier bits
• 2112 user-programmable OTP bits
— Absolute write protection: V
PP
= V
SS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Password Access feature
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Architecture
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Blank Check to verify an erased block
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— Numonyx™ QUAD+ SCSP (256, 512-Mbit)
— 16-bit wide data bus
Voltage and Power
— V
CC
(core) voltage: 1.7 V – 2.0 V
— V
CCQ
(I/O) voltage: 1.7 V – 3.6 V
— Standby current: 65 µA (Typ) for 256-Mbit;
— 52 MHz continuos synchronous read current:
21mA (Typ)/24mA(Max)
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ X process technology
Datasheet
1
Apr 2009
Order Number: 320002-08
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Apr 2009
Order Number: 320002-08
P30 - 65 nm
Contents
1.0
Functional Description
............................................................................................... 5
1.1
Introduction ....................................................................................................... 5
1.2
Overview ........................................................................................................... 5
1.3
Virtual Chip Enable Description.............................................................................. 6
1.4
Memory Maps ..................................................................................................... 7
Package Information
................................................................................................. 8
2.1
56-Lead TSOP..................................................................................................... 8
2.2
64-Ball Easy BGA Package .................................................................................. 10
2.3
QUAD+ SCSP Packages ...................................................................................... 11
Ballouts
................................................................................................................... 13
Signals
.................................................................................................................... 16
4.1
Dual-Die Configurations ..................................................................................... 18
Bus Operations
........................................................................................................ 19
5.1
Reads .............................................................................................................. 19
5.2
Writes.............................................................................................................. 19
5.3
Output Disable .................................................................................................. 19
5.4
Standby ........................................................................................................... 20
5.5
Reset............................................................................................................... 20
Command Set
.......................................................................................................... 21
6.1
Device Command Codes ..................................................................................... 21
6.2
Device Command Bus Cycles .............................................................................. 22
Read
7.1
7.2
7.3
7.4
Operation........................................................................................................
25
Asynchronous Page-Mode Read ........................................................................... 25
Synchronous Burst-Mode Read............................................................................ 25
Read Device Identifier........................................................................................ 26
Read CFI .......................................................................................................... 26
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Program Operation
.................................................................................................. 27
8.1
Word Programming ........................................................................................... 27
8.2
Buffered Programming ....................................................................................... 27
8.3
Buffered Enhanced Factory Programming.............................................................. 28
8.4
Program Suspend .............................................................................................. 30
8.5
Program Resume............................................................................................... 31
8.6
Program Protection ............................................................................................ 31
Erase Operations
..................................................................................................... 32
9.1
Block Erase ...................................................................................................... 32
9.2
Blank Check ..................................................................................................... 32
9.3
Erase Suspend .................................................................................................. 33
9.4
Erase Resume................................................................................................... 33
9.5
Erase Protection ................................................................................................ 33
9.0
10.0 Security Modes
........................................................................................................ 34
10.1 Block Locking.................................................................................................... 34
10.2 Selectable One-Time Programmable Blocks ........................................................... 36
10.3 Password Access ............................................................................................... 36
11.0 Registers
................................................................................................................. 37
11.1 Read Status Register ......................................................................................... 37
11.2 Read Configuration Register................................................................................ 38
Datasheet
3
Apr 2009
Order Number: 320002-08
P30 - 65 nm
11.3
One-Time-Programmable (OTP) Registers .............................................................44
12.0 Power and Reset Specifications
...............................................................................47
12.1 Power-Up and Power-Down .................................................................................47
12.2 Reset Specifications ...........................................................................................47
12.3 Power Supply Decoupling ....................................................................................48
13.0 Maximum Ratings and Operating Conditions
............................................................49
13.1 Absolute Maximum Ratings .................................................................................49
13.2 Operating Conditions..........................................................................................49
14.0 Electrical Specifications
...........................................................................................50
14.1 DC Current Characteristics ..................................................................................50
14.2 DC Voltage Characteristics ..................................................................................51
15.0 AC Characteristics
....................................................................................................52
15.1 AC Test Conditions.............................................................................................52
15.2 Capacitance ......................................................................................................53
15.3 AC Read Specifications .......................................................................................53
15.4 AC Write Specifications .......................................................................................58
16.0 Program and Erase Characteristics...........................................................................62
17.0 Ordering Information...............................................................................................63
17.1 Discrete Products...............................................................................................63
17.2 SCSP Products...................................................................................................64
A
Supplemental Reference Information.......................................................................65
A.1
Common Flash Interface Tables ...........................................................................65
A.2
Flowcharts ........................................................................................................77
A.3
Write State Machine ...........................................................................................85
Conventions - Additional Information
......................................................................89
B.1
Conventions......................................................................................................89
B.2
Acronyms .........................................................................................................89
B.3
Nomenclature....................................................................................................90
Revision History.......................................................................................................91
B
C
Datasheet
4
Apr 2009
Order Number: 320002-08
P30-65nm
1.0
1.1
Functional Description
Introduction
This document provides information about the Numonyx
TM
StrataFlash
®
Embedded
Memory (P30-65nm) product and describes its features, operations, and specifications.
The Numonyx
TM
StrataFlash
®
Embedded Memory (P30-65nm) is the latest generation
of Numonyx™ StrataFlash
®
memory devices. P30-65nm device will be offered in 64-
Mbit up through 2-Gbit densities. This document covers specifically 256-Mbit and 512-
Mbit (256M/256M) product information. Benefits include more density in less space,
high-speed interface device, and support for code and data storage. Features include
high-performance synchronous-burst read mode, fast asynchronous access times, low
power, flexible security options, and three industry-standard package choices. The P30-
65nm product family is manufactured using Numonyx™ 65nm ETOX™ X process
technology.
1.2
Overview
This section provides an overview of the features and capabilities of the P30-65nm.
The P30-65nm family devices provides high performance at low voltage on a 16-bit
data bus. Individually erasable memory blocks are sized for optimum code and data
storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the Read Configuration Register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-
supplied clock signal. A WAIT signal provides easy CPU-to-flash memory
synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the P30-65nm supports read operations with V
CC
at 1.8 V, and erase
and program operations with V
PP
at 1.8 V or 9.0 V. Buffered Enhanced Factory
Programming (BEFP) provides the fastest flash array programming performance with
V
PP
at 9.0 V, which increases factory throughput. With V
PP
at 1.8 V, VCC and VPP can be
tied together for a simple, ultra low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when V
PP
≤
V
PPLK
.
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The P30-65nm protection register allows unique flash device identification that can be
used to increase system security. The individual Block Lock feature provides zero-
latency block locking and unlocking. The P30-65nm device adds enhanced protection
via Password Access; this new feature allows write and/or read access protection of
user-defined blocks. In addition, the P30-65nm device also provides backward
compatible One-Time Programmable (OTP) security feature.
Datasheet
5
Apr 2009
Order Number: 320002-08
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