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874005AG

Description
PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Categorylogic    logic   
File Size556KB，15 Pages
ManufacturerIDT (Integrated Device Technology)
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874005AG Overview

PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24

874005AG Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts24
Reach Compliance Codenot_compliant
ECCN codeEAR99
series874005
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length7.8 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals24
Actual output times5
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.09 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width4.4 mm
minfmax98 MHz

874005AG Preview

PCI Express™ Jitter Attenuator
ICS874005
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS874005 is a high performance Differential-to-LVDS
Jitter Attenuator designed for use in PCI Express systems.
In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated from a
low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be
required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874005 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 400kHz provides an intermediate
bandwidth that can easily track triangular spread profiles,
while providing good jitter attenuation. The 800kHz
bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be
as good as the lower bandwidth modes. Because some
2.5Gb serdes have x20 multipliers while others have than
x25 multipliers, the 874005 can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output)
using the F_SEL pins.
The ICS874005 uses IDT’s 3
rd
Generation FemtoClock
®
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
F
EATURES
•
Five differential LVDS output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 160MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 30ps (maximum)
•
3.3V operating supply
•
3 bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
B
LOCK
D
IAGRAM
OEA
Pullup
F_SELA
Pulldown
BW_SEL
Float
0=
~200kHz
Float = ~400kHz
1=
~800kHz
QA0
P
IN
A
SSIGNMENT
nQB2
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
V
DDA
F_SELA
V
DD
OEA
nQB0
QB1
F_SELA
0 5
(default)
1 4
nQA0
QA1
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640MHz
F_SELB
0 5
(default)
1 4
nQA1
QB0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QB2
V
DDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
ICS874005
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
M = 5
(fixed)
nQB1
QB2
G Package
Top View
nQB2
F_SELB
Pulldown
MR
Pulldown
OEB
Pullup
ICS874005AG REVISION B JANUARY 12, 2012
1
©
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS ™ JITTER ATTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 24
2, 3
4, 23
5, 6
7
Name
nQB2, QB2
nQA1, QA1
V
DDO
QA0, nQA0
MR
Type
Output
Output
Power
Output
Input
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
Pulldown
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pullup/
PLL Bandwidth input. See Table 3B.
Pulldown
Analog supply pin.
Frequency select pin for QAx,nQAx outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
Pullup
active. When LOW, the QAx,nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
Pullup
active. When LOW, the QBx,nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Frequency select pin for QBx,nQBx outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
8
9
10
11
12
13
14
15, 16
17
18
19, 20
21, 22
BW_SEL
V
DDA
F _S E LA
V
DD
OEA
C LK
nCLK
GND
OEB
F _S E LB
nQB0, QB0
nQB1, QB1
Input
Power
Input
Power
Input
Input
Input
Power
Input
Input
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA/OEB
0
1
HiZ
Enabled
Outputs
QAx/nQAx
QBx/nQBx
HiZ
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
/PLL B
YPASS
C
ONTROL
Inputs
PLL_BW
0
1
Float
PLL
Bandwidth
~200kHz
~800kHz
~400kHz
ICS874005AG REVISION B JANUARY 12, 2012
2
©
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS ™ JITTER ATTENUATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
85
15
115
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
Input High Voltage
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
Input Low Voltage
Input Mid Voltage
Input High Current
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
BW_SEL
OEA, OEB
F_SELA, F_SELB
MR, BW_SEL
BW_SEL,
OEA, OEB
MR,
F_SELA, F_SELB
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
V
DD
/2 - 0.1
Test Conditions
Minimum
2
V
DD
- 0.4
-0.3
0.8
0.4
V
DD
/2 + 0.1
5
150
Typical
Maximum
V
DD
+ 0.3
Units
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
V
IL
V
IM
I
IH
I
IL
Input Low Current
ICS874005AG REVISION B JANUARY 12, 2012
3
©
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS ™ JITTER ATTENUATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
C LK
nCLK
C LK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-5
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
μ
A
μ
A
μ
A
μ
A
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
1.35
Test Conditions
Minimum
275
Typical
375
Maximum
485
50
1.5
50
Units
mV
mV
V
mV
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
jit(cc)
t
sk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter, NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
Test Conditions
Minimum
98
15
Typical
Maximum
160
30
90
550
52
Units
MHz
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
ICS874005AG REVISION B JANUARY 12, 2012
4
©
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS ™ JITTER ATTENUATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD,
V
DDO
V
DDA
V
DD
3.3V±5%
POWER SUPPLY
Float GND
+
–
Qx
SCOPE
nCLK
V
PP
LVDS
nQx
Cross Points
V
CMR
CLK
GND
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQA0, nQA1
nQB0:nQB2
QA0, QA1
QB0:QB2
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
C
YCLE
-
TO
-C
YCLE
J
ITTER
80%
Clock
Outputs
20%
t
R
t
F
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DD
out
DC Input
LVDS
100
V
OD
/Δ V
OD
out
➤
out
V
OS
/Δ V
OS
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
O
FFSET
V
OLTAGE
S
ETUP
ICS874005AG REVISION B JANUARY 12, 2012
5
©
2012 Integrated Device Technology, Inc.
➤
➤
➤
➤
t
cycle n
t
cycle
n+1
➤
➤
nQy
Qy
tsk(o)
O
UTPUT
S
KEW
nQA0, nQA1
nQB0:nQB2
80%
V
SW I N G
20%
QA0, QA1
QB0:QB2
t
PW
t
PERIOD
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
DD
out
➤
DC Input
LVDS
➤
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874005AG Related Products

874005AG 874005AGT
Description PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts 24 24
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
series 874005 874005
Input adjustment DIFFERENTIAL DIFFERENTIAL
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0
length 7.8 mm 7.8 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 1 1
Number of functions 1 1
Number of terminals 24 24
Actual output times 5 5
Maximum operating temperature 70 °C 70 °C
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 240 240
Certification status Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.09 ns 0.09 ns
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 20 20
width 4.4 mm 4.4 mm
minfmax 98 MHz 98 MHz

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