256Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H64M4 – 16 Meg x 4 x 4 banks
MT47H32M8 – 8 Meg x 8 x 4 banks
MT47H16M16 – 4 Meg x 16 x 4 banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= 1.8V ±0.1V, V
DDQ
= 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Automotive temperature (AT) option
RoHS-compliant
Supports JEDEC clock jitter specification
Options
1
• Configuration
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• FBGA package (Pb-free)
– 60-ball FBGA (8mm x 12mm) x4, x8
– 84-ball FBGA (8mm x 14mm) x16
• FBGA package (lead solder)
– 60-ball FBGA (8mm x 12mm) x4, x8
– 84-ball FBGA (8mm x 14mm) x16
• Timing – cycle time
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
– 5.0ns @ CL = 3 (DDR2-400)
• Self refresh
– Standard
– Low-power
• Operating temperature
– Commercial (0°C T
C
+85°C)
– Industrial (–40°C T
C
+95°C;
–40°C T
A
+85°C)
– Automotive (–40°C T
C
, T
A
+105°C)
• Revision
Note:
Marking
64M4
32M8
16M16
BP
BG
FP
FG
-3
-37E
-5E
None
L
None
IT
AT
:B
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed Grade
-3
-37E
-5E
CL = 3
400
400
400
CL = 4
533
533
400
CL = 5
667
n/a
n/a
t
RC
(ns)
55
55
55
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x4, x8, x16 DDR2 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
64 Meg x 4
16 Meg x 4 x 4 banks
8K
A[12:0] (8K)
BA[1:0] (4)
A[11, 9:0] (2K)
32 Meg x 8
8 Meg x 8 x 4 banks
8K
A[12:0] (8K)
BA[1:0] (4)
A[9:0] (1K)
16 Meg x 16
4 Meg x 16 x 4 banks
8K
A[12:0] (8K)
BA[1:0] (4)
A[8:0] (512)
Figure 1: 256Mb DDR2 Part Numbers
Example Part Number: MT47H32M8BP-3 :B
-
MT47H
Configuration
Package
Speed
:
Revision
^
Configuration
64 Meg x 4
32 Meg x 8
16 Meg x 16
Package
Pb-free
84-ball 8mm x 14mm FBGA
60-ball 8mm x 12mm FBGA
Lead solder
84-ball 8mm x 14mm FBGA
60-ball 8mm x 12mm FBGA
FG
FP
BG
BP
-3
Speed Grade
tCK = 3ns, CL = 5
64M4
32M8
16M16
:B
Revision
L Low power
IT Industrial temperature
AT Automotive temperature
-37E tCK = 3.75ns, CL = 4
-5E tCK = 5ns, CL = 3
Note:
1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR2 SDRAM
Features
Contents
State Diagram .................................................................................................................................................. 8
Functional Description ..................................................................................................................................... 9
Industrial Temperature ................................................................................................................................. 9
Automotive Temperature ............................................................................................................................ 10
General Notes ............................................................................................................................................ 10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 14
Packaging ...................................................................................................................................................... 18
Package Dimensions ................................................................................................................................... 18
FBGA Package Capacitance ......................................................................................................................... 20
Electrical Specifications – Absolute Ratings ..................................................................................................... 21
Temperature and Thermal Impedance ........................................................................................................ 21
Electrical Specifications – I
DD
Parameters ........................................................................................................ 24
I
DD
Specifications and Conditions ............................................................................................................... 24
I
DD7
Conditions .......................................................................................................................................... 24
AC Timing Operating Specifications ................................................................................................................ 27
AC and DC Operating Conditions .................................................................................................................... 39
ODT DC Electrical Characteristics ................................................................................................................... 40
Input Electrical Characteristics and Operating Conditions ............................................................................... 41
Output Electrical Characteristics and Operating Conditions ............................................................................. 44
Output Driver Characteristics ......................................................................................................................... 46
Power and Ground Clamp Characteristics ....................................................................................................... 50
AC Overshoot/Undershoot Specification ......................................................................................................... 51
Input Slew Rate Derating ................................................................................................................................ 53
Commands .................................................................................................................................................... 66
Truth Tables ............................................................................................................................................... 66
DESELECT ................................................................................................................................................. 70
NO OPERATION (NOP) ............................................................................................................................... 71
LOAD MODE (LM) ...................................................................................................................................... 71
ACTIVATE .................................................................................................................................................. 71
READ ......................................................................................................................................................... 71
WRITE ....................................................................................................................................................... 71
PRECHARGE .............................................................................................................................................. 72
REFRESH ................................................................................................................................................... 72
SELF REFRESH ........................................................................................................................................... 72
Mode Register (MR) ........................................................................................................................................ 72
Burst Length .............................................................................................................................................. 73
Burst Type .................................................................................................................................................. 74
Operating Mode ......................................................................................................................................... 74
DLL RESET ................................................................................................................................................. 74
Write Recovery ........................................................................................................................................... 75
Power-Down Mode ..................................................................................................................................... 75
CAS Latency (CL) ........................................................................................................................................ 76
Extended Mode Register (EMR) ....................................................................................................................... 77
DLL Enable/Disable ................................................................................................................................... 78
Output Drive Strength ................................................................................................................................ 78
DQS# Enable/Disable ................................................................................................................................. 78
RDQS Enable/Disable ................................................................................................................................. 78
Output Enable/Disable ............................................................................................................................... 78
On-Die Termination (ODT) ......................................................................................................................... 79
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR2 SDRAM
Features
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 79
Posted CAS Additive Latency (AL) ................................................................................................................ 79
Extended Mode Register 2 (EMR2) ................................................................................................................... 81
Extended Mode Register 3 (EMR3) ................................................................................................................... 82
Initialization .................................................................................................................................................. 83
ACTIVATE ...................................................................................................................................................... 86
READ ............................................................................................................................................................. 88
READ with Precharge .................................................................................................................................. 92
READ with Auto Precharge .......................................................................................................................... 94
WRITE ........................................................................................................................................................... 99
PRECHARGE ................................................................................................................................................. 109
REFRESH ...................................................................................................................................................... 110
SELF REFRESH .............................................................................................................................................. 111
Power-Down Mode ........................................................................................................................................ 113
Precharge Power-Down Clock Frequency Change ........................................................................................... 120
Reset ............................................................................................................................................................. 121
CKE Low Anytime ...................................................................................................................................... 121
ODT Timing .................................................................................................................................................. 123
MRS Command to ODT Update Delay ........................................................................................................ 125
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR2 SDRAM
Features
List of Figures
Figure 1: 256Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 64 Meg x 4 Functional Block Diagram ............................................................................................... 11
Figure 4: 32 Meg x 8 Functional Block Diagram ............................................................................................... 12
Figure 5: 16 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15
Figure 8: 84-Ball, FBGA Package (8mm x 14mm) – x16 ..................................................................................... 18
Figure 9: 60-Ball, FBGA Package (8mm x 12mm) – x4, x8 ................................................................................. 19
Figure 10: Example Temperature Test Point Location ...................................................................................... 22
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 41
Figure 12: Differential Input Signal Levels ...................................................................................................... 42
Figure 13: Differential Output Signal Levels .................................................................................................... 44
Figure 14: Output Slew Rate Load .................................................................................................................. 45
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 46
Figure 16: Full Strength Pull-Up Characteristics .............................................................................................. 47
Figure 17: Reduced Strength Pull-Down Characteristics .................................................................................. 48
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 49
Figure 19: Input Clamp Characteristics .......................................................................................................... 50
Figure 20: Overshoot ..................................................................................................................................... 51
Figure 21: Undershoot ................................................................................................................................... 51
Figure 22: Nominal Slew Rate for
t
IS ............................................................................................................... 56
Figure 23: Tangent Line for
t
IS ........................................................................................................................ 56
Figure 24: Nominal Slew Rate for
t
IH .............................................................................................................. 57
Figure 25: Tangent Line for
t
IH ....................................................................................................................... 57
Figure 26: Nominal Slew Rate for
t
DS ............................................................................................................. 62
Figure 27: Tangent Line for
t
DS ...................................................................................................................... 62
Figure 28: Nominal Slew Rate for
t
DH ............................................................................................................. 63
Figure 29: Tangent Line for
t
DH ..................................................................................................................... 63
Figure 30: AC Input Test Signal Waveform Command/Address Balls ................................................................ 64
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 64
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 65
Figure 33: AC Input Test Signal Waveform (Differential) .................................................................................. 65
Figure 34: MR Definition ............................................................................................................................... 73
Figure 35: CL ................................................................................................................................................. 76
Figure 36: EMR Definition ............................................................................................................................. 77
Figure 37: READ Latency ............................................................................................................................... 80
Figure 38: WRITE Latency .............................................................................................................................. 80
Figure 39: EMR2 Definition ........................................................................................................................... 81
Figure 40: EMR3 Definition ........................................................................................................................... 82
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 83
Figure 42: Example: Meeting
t
RRD (MIN) and
t
RCD (MIN) .............................................................................. 86
Figure 43: Multibank Activate Restriction ....................................................................................................... 87
Figure 44: READ Latency ............................................................................................................................... 89
Figure 45: Consecutive READ Bursts .............................................................................................................. 90
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 91
Figure 47: READ Interrupted by READ ............................................................................................................ 92
Figure 48: READ-to-WRITE ............................................................................................................................ 92
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 93
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 93
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2003 Micron Technology, Inc. All rights reserved.
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