SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
MBM29BS/BT32LF
-18/25
(Continued)
The device supports Enhanced V
CCQ
to offer up to 3 V compatible inputs and outputs(MBM29BS32LF:1.8V V
CCQ
,
MBM29BT32LF:3.0V V
CCQ
). 12.0V V
PP
and 5.0V V
CC
are not required for write or erase operations. The device
can also be programmed in standard EPROM programmers.
The device provides truly high performance non-volatile memory solution. The device offers fast burst access
frequency of 54MHz with initial access times of 106ns, allowing operation of high-speed microprocessors without
wait states. To eliminate bus connection the device has separate chip enable (CE), write enable (WE), address
valid (AVD) and output enable (OE) controls. For burst operations, the device additionally requires Ready (RDY),
and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of
microprocessors/ microcontrollers for high performance read operations. The burst read mode feature gives
system designers flexibility in the interface to the device. The user can preset the burst length and wrap through
the same memory space. At 54 MHz, the device provides a burst access of 13.5 ns with a latency of 106 ns at
30 pF.
The dual operation function provides simultaneous operation by dividing the memory space into four banks. The
device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is command set compatible with JEDEC standard E
2
PROMs. Commands are written to the command
register using standard microprocessor write timing. Register contents serve as inputs to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0V and 12.0V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 second.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 0.2 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The Enhanced V
I/O
(V
CCQ
) feature allows the output voltage generated on the device to be determined based on
the V
I/O
level. This feature allows this device to operate in the 1.8 V and 3.0 V I/O environment, driving and
receiving signals to and from other 1.8 V and 3.0 V devices on the same bus.
The device features single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, output pin. Once the end of a program or erase cycle has been comleted, the
device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Retired Product DS05-20913-3E_August 2, 2007
5
Embedded System
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