DATASHEET
VIDEO GENLOCK PLL
Description
The IDT9173B provide the analog PLL circuit blocks to
implement a frequency multiplier. Because the device is
configured to use an external divider in the PLL clock
feedback path, a large divider can be used to result in a
large frequency multiplication ratio. This is useful when
using a low frequency input clock to generate a high
frequency output clock. The IDT9173B contains a phase
detector, charge pump, loop filter, and voltage-controlled
oscillator (VCO). The ICS674-01 can be used as the
external feedback divider.
A common application of the IDT9173B is the
implementation of a video genlock circuit. Because of this,
the IDT9173B inputs operate on the negative-going clock
edge.
The IDT9173B is pin and function compatible to the
AV9173-01/15.
IDT9173B
Features
•
Phase-detector/VCO circuit block
•
Ideal for genlock system
•
Reference clock range 12 kHz to 1 MHz for full output
clock range
•
Output clock range of 1.25 to 75 MHz (-01), and 0.625 to
37.5 MHz (-15). See “Allowable Input Frequency to
Output Frequency” table for conditions
•
•
•
•
On-chip loop filter
Single 5 V power supply
Low power CMOS technology
8-pin SOIC package
Block Diagram
IDT™
VIDEO GENLOCK PLL
1
IDT9173B
REV B 111209
IDT9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Using the IDT9173B in Genlock Applications
Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The IDT9173B integrates the analog
blocks which make the task much easier.
In the complete video genlock circuit, the primary function of
the IDT9173B is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application
is illustrated in Figure 1. The input reference signal for this
circuit is the horizontal synchronization (H-SYNC) signal. If
a composite video reference source is being used, the
h-sync pulses must be separated from the composite signal.
A video sync separator circuit, such as the National
Semiconductor LM1881, can be used for this purpose.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880
pixel clocks are desired per h-sync pulse, then the divider
ratio is set to 880. Hence, together the h-sync frequency and
external divider ratio establish the dot clock frequency:
f
OUT
= f
IN
x N where N is external divide ratio
Both input pins IN and FBIN respond only to negative-going
clock edges of the input signal. The H-SYNC signal must be
constant frequency in the 12 kHz to 1 MHz range and stable
(low clock jitter) for creation of a stable output clock.
The output hook-ups of the IDT9173B are dictated by the
desired dot clock frequency. The primary consideration is
the internal VCO which operates over a frequency range of
10 MHz to 75 MHz. Because of the selectable VCO output
divider and the additional divider on output CLK2, four
distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
FS0
State
0
0
1
1
Output
Used
CLK1
CLK2
CLK1
CLK2
Frequency/Range
IDT9173B-01
10 to 75 MHz
5 to 37.5 MHz
2.5 to 18.75 MHz
1.25 to 9.375 MHz
Frequency/Range
IDT9173B-15
5 to 37.5 MHz
2.5 to 18.75 MHz
1.25 to 9.375 MHz
0.625 to 4.6875 MHz
Note that both outputs, CLK1 and CLK2, are available
during operation even though only one is fed back via the
external clock divider.
Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
When unused, inputs FS0 and OE must be tied to either
GND (logic low) or VDD (logic high).
Figure 1: Typical Application of IDT9173B in a Video Genlock System
IDT™
VIDEO GENLOCK PLL
3
IDT9173B
REV B 111209
IDT9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT9173B. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
Storage Temperature
Voltage on I/O Pins referenced to GND
Junction Temperature
Soldering Temperature
Power Dissipation
7V
-65 to +150° C
Rating
GND - 0.5 V to VDD + 0.5 V
125° C
260° C
0.5 Watts
Recommended Operation Conditions
Parameter
Operating Temperature under Bias
Power Supply Voltage (measured with respect to
GND)
Min.
-0
+4.75
Typ.
+5 V
Max.
+70
+5.25
Units
°
C
V
IDT™
VIDEO GENLOCK PLL
4
IDT9173B
REV B 111209
京公网安备 11010802033920号
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