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MT47H128M4B6-3

Description
DDR DRAM, 128MX4, 0.45ns, CMOS, PBGA60
Categorystorage    storage   
File Size9MB,129 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT47H128M4B6-3 Overview

DDR DRAM, 128MX4, 0.45ns, CMOS, PBGA60

MT47H128M4B6-3 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
package instructionFBGA, BGA60,9X11,32
Reach Compliance Codecompliant
Maximum access time0.45 ns
Maximum clock frequency (fCLK)333 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B60
JESD-609 codee3
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width4
Humidity sensitivity level1
Number of terminals60
word count134217728 words
character code128000000
organize128MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA60,9X11,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)225
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Continuous burst length4,8
Maximum standby current0.007 A
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal surfaceMATTE TIN
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
512Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
Features
V
DD
= +1.8V ±0.1V, V
DDQ
= +1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Automotive temperature (AT) option
RoHS-compliant
Supports JEDEC clock jitter specification
Options
1
Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
FBGA package (Pb-free) – x16
84-ball FBGA (8mm x 12.5mm) Rev. F
FBGA package (Pb-free) – x4, x8
60-ball FBGA (8mm x 10mm) Rev. F
FBGA package (lead solder) – x16
84-ball FBGA (8mm x 12.5mm) Rev. F
FBGA package (lead solder) – x4, x8
60-ball FBGA (8mm x 10mm) Rev. F
Timing – cycle time
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 4 (DDR2-667)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Self refresh
Standard
Low-power
Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C;
–40°C
T
A
85°C)
Automotive (–40°C
T
C
, T
A
105°C)
Revision
Note:
Marking
128M4
64M8
32M16
HR
CF
HW
JN
-25E
-25
-3E
-3
-37E
None
L
None
IT
AT
:F
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. O 7/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2004
Micron Technology, Inc. All rights reserved.
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