FIFO – HX6409/HX6218/HX6136
First-In First-Out Memory
HX6409/HX6218/HX6136
The HX6409, HX6218, and HX6136 are high speed,
low power, first-in first-out memories with clocked read
and write interfaces. The HX6409 is a 4096-word by 9-
bit memory array; the HX6218 is a 2048-word by 18-bit
memory array; and the HX6136 is a 1024-word by 36-
bit memory array. The FIFOs support width expansion
while depth expansion requires external logic control
using state machine techniques. Features include
programmable parity control, an empty/full flag, a
quarter/three quarter full flag, a half full flag and an
error flag.
Honeywell’s FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and
communications buffering.
Input ports are controlled by a free running clock (CKW)
and a write-enable pin ENW. When ENW is asserted,
data is written into the FIFO on the rising edge of the
CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle.
The output port is controlled in a similar manner by a
freerunning read clock (CKR) and a read enable pin
(ENR). In addition, the three FIFOs have an output
enable pin (OE) and a master reset pin (MR). The read
(CKR) and write (CKW) clocks may be tied together for
Honeywell’s enhanced SOI RICMOS™ IV (Radiation
Insensitive CMOS) technology is radiation hardened
through the use of advanced and proprietary design,
layout and process hardening techniques. The FIFO is
fabricated with Honeywell’s radiation-hardened
technology, and is designed for use in systems
operating in radiation environments. The SOI
RICMOS™ IV process is a 5-volt, SOI CMOS
technology with a 150 Å gate oxide and a minimum
drawn feature size of 0.8µm, (0.65µm effective gate
length—L
eff
). Additional features include tungsten via
plugs, Honeywell’s proprietary SHARP planarization
process, and a lightly doped drain (LDD) structure.
single-clock operation or the two clocks may be run
independently for asynchronous read/write applications.
Clock frequencies up to 28 MHz are achievable in the
three configurations.
FEATURES
1K x 36, 2K x 18, 4K x 9
configurations
Fabricated with RICMOS™ IV
Silicon on Insulator (SOI) 0.8
µm process (Leff = 0.65µm)
Total dose hardness through
1x10
6
rad(Si)
Neutron hardness through
1x10
14
cm
-2
Dynamic and static transient
upset hardness through 1x10
9
rad(Si)/s
Dose rate survivability through
1x10
11
rad(Si)/s
Soft error rate of <1x10
-10
upsets/bit-day
No latchup
Read/write cycle times
36 ns (-55°to 125°C)
Expandable in Width
Empty, full, half full, 1/4 full,
¾ full, error flags
Parity generation/checking
Fully asynchronous with
simultaneous read and write
operation
Output enable (OE)
CMOS or TTL compatible I/O
Single 5V ±10% power supply
Various flat pack options
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1
FIFO – HX6409/HX6218/HX6136
LOGIC BLOCK DIAGRAM
FLAG DECODE TABLE
Word Count
EF_Fault
0
1
1
1
1
1
1
0
E/F
0
0
1
1
1
1
0
0
QF/TQF
0
0
0
1
1
0
0
0
HF
1
1
1
1
0
0
0
0
State
Empty fault (Enabled Read
when Empty)
Empty
Less than or equal to ¼ full
Less than or equal to ½ full
Greater than ½ full
Greater than or equal to ¾ full
Full
Full fault (Enabled Write
when Full)
4K x 9
0
0
1 to 1024
1025 to 2048
2049 to 3071
3072 to 4095
4096
4096
2K x 18
0
0
1 to 512
513 to 1024
1025 to 1535
1536 to 2047
2048
2048
1K x 36
0
0
1 to 256
257 to 512
513 to 767
768 to 1023
1024
1024
2
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FIFO – HX6409/HX6218/HX6136
SIGNAL DEFINITIONS
Signal Name
D: 0 – 35
Q: 0 – 35
ENW
ENR
CKW
CKR
HF
E/F
QF/TQF
I/O
I
O
I
I
I
I
O
O
O
Description
Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when
ENW is active and the FIFO is not full.
Data Outputs: Data Outputs are read out of the FIFO memory and updated on the
rising edge of CKR when ENR is active and the FIFO is not Empty. The Data Outputs
are in a high impedance state if OE is not active.
Enable Write: An active low signal that enables the write of the Data Inputs on the
CKW rising edge (if FIFO is not full).
Enable Read: An active low signal that enables the read and update of the Data
Outputs on the CKR rising edge (if FIFO is not empty).
Write Clock: The rising edge clocks data into the FIFO when ENW is low (active). On
the rising edge, this signal also updates the Half Full, ¾ Full, Full, and Full Fault Flags.
Read Clock: The rising edge clocks data out of the FIFO when ENR is low (active). On
the rising edge, this signal also updates the ¼ Full, Empty, and Empty Fault Flags.
Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is
greater than half full.
Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated
on the rising edge of CKW.
¼ Full or ¾ Full Flag: ¼ Full is updated on the rising edge of CKR, and ¾ Full is
updated on the rising edge of CKW. ¼ Full signifies 256 or less words in the 1K x 36
FIFO and ¾ Full signifies 256 words or less until a full condition.
Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full
Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already
empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault
condition is detected, the Fault Flag remains latched until the empty or full condition is
removed.
Master Reset: Active low signal which, when active, resets device to empty condition
Output Enable: Active low signal which, when active, enables low impedance Data
Outputs, Q: 0 – 35
EF_Fault
MR
OE
O
I
I
PROGRAMMABLE PARITY OPTIONS
D2
O
I
I
I
I
D1
X
O
O
I
I
D0
X
O
I
O
I
Conditions
Parity Disabled
Generate Even Parity, Q8, Q17, Q26, Q35
Generate Odd Parity, Q8, Q17, Q26, Q35
Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal
Check for Odd Parity, Error on Q8, Q17, Q35, Error is a Low Signal
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3
FIFO – HX6409/HX6218/HX6136
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
All FIFO configurations will meet all stated functional
and electrical specifications over the entire operating
temperature range after the specified total ionizing
radiation dose. All electrical and timing performance
parameters will remain within specifications after
rebound at VDD = 5.5 V and T = 125°C extrapolated to
ten years of operation. Total dose hardness is assured
by wafer level testing of process monitor transistors and
product using 10 KeV X-ray and Co60 radiation
sources. Transistor gate threshold shift correlations
have been made between 10 KeV X-rays applied at a
dose rate of 1x10
5
rad(Si)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
Each FIFO configuration is capable of writing, reading
and retaining stored data during and after exposure to a
transient ionizing radiation pulse of
≤50
ns duration up
to 1x10
9
rad(Si)/s, when applied under recommended
operating
conditions. To ensure validity of all specified
performance parameters before, during, and after
radiation (timing degradation during transient pulse
radiation (timing degradation during transient pulse
radiation is
≤10%),
it is suggested that stiffening
capacitance be placed near the package VDD and
VSS, with a maximum inductance between the package
(chip) and stiffening capacitor of 0.7nH per part. If there
are no operate-through or valid stored data
requirements, typical circuit board mounted de-coupling
capacitors are recommended.
Each FIFO will meet any functional or electrical
specification after exposure to a radiation pulse of
≤50
ns duration up to 1x10
11
rad(Si)/s, when applied under
recommended operating conditions. Note the current
conducted by the inputs, outputs and power supply
during the pulse may significantly exceed the normal
operating levels. The application design must
accommodate these effects.
Neutron Radiation
Each FIFO configuration will meet any functional or
timing specification after a total neutron fluence of up to
1x10
14
cm
-2
applied under recommended operating or
storage conditions. This assumes equivalent neutron
energy of 1 MeV.
Soft Error Rate
This FIFO configuration has a soft error rate (SER)
performance of <1x10
-10
upsets/bit-day, under
recommended operating conditions. This hardness
level is defined by the Adams 90% worst-case cosmic
ray environment.
Latchup
This FIFO configuration will not latch up due to any of
the above radiation exposure conditions when applied
under recommended operating conditions. Fabrication
with the SOI substrate with its oxide isolation ensures
latchup immunity.
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FIFO – HX6409/HX6218/HX6136
RADIATION-HARDNESS RATINGS
(1)
Parameter
Limits
(2)
Units
Test Conditions
6
Total Dose
>1x10
rad(Si)
T
A
=25°C
9
Transient Dose Rate Upset
>1x10
rad(Si)/s
Pulse width
≤50ns
11
Transient Dose Rate Survivability
>1x10
rad(Si)/s
Pulse width
≤50ns,
X-ray, VDD=6.0 V, T
A
=25°C
-10
Soft Error Rate
<1x10
upsets/bit-day
T
A
=125°C, Adams 90% worst case environment
14
2
Neutron Fluence
>1x10
N/cm
1 MeV equivalent energy, Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD= 4.5V to 5.5V, TA = 55˚C to 125˚C.
ABSOLUTE MAXIMUM RATINGS
(1)
Rating
Units
Symbol
Parameter
Min
Max
VDD
Supply Voltage Range (2)
-0.5
6.5
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
˚C
TSOLDER
Soldering Temperature (5 seconds)
270
˚C
PD
Maximum Power Dissipation
(3)
2.5
W
IOUT
DC or Average Output Current
2.5
mA
VPROT
ESD Input Protection Voltage
(4)
2000
V
ΘJC
Thermal Resistance (Jct-to-Case)
5
˚C/W
TJ
Junction Temperature
175
˚C
(1) Stesses in excess of those listed above may result in permanent damage. These are stress ratings only, and
operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may
affect device reliability.
(2) Voltage referenced to VSS.
(3) FIFO power dissipation (IDDSB + IDDOP) plus FIFO output driver power dissipation due to external loading
must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC
certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
4.5
-55
-0.3
Description
Typ
5.0
25
Max
5.5
125
VDD+0.3
Units
V
˚C
V
CAPACITANCE
(1)
Worst Case
Symbol Parameter
Units
Typical
(1)
Min
Max
CI
Input Capacitance
7
pF
CO
Output Capacitance
9
pF
(1) This parameter is tested during design characterization only.
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
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