Maintenance only
Features
Description
Addressing
The UD61256 is a dynamic Write-
Read-memory with random access.
FPM facilitates faster data operation
with predefined row address. Via 9
address inputs the 18 address bits
are transmitted into the internal
address memories in a time-multi-
plex operation. The falling RAS-
edge takes over the row address.
During RAS Low, the column
address together with the CAS
signal are taken over. The selection
of one or more memory circuits can
be made by activation of the RAS
input.
Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
cycle.
Both CAS-controlled and W-control-
led Write cycles are possible with
activated RAS signal.
UD61256
256K x 1 DRAM
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic „0“ or „1“.
Q is then valid until CAS returns into
to inactive state (HIGH).
The memory cycle being a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state („0“ or „1“).
After the access time the contents of
the selected cell is available, except
for the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
F
Dynamic random access memory
F
F
F
F
F
F
F
F
F
F
262144 x 1 bit manufactured
using a CMOS technology
RAS access times 70 ns, 80 ns
TTL-compatible
Three-state output
256 refresh cycles
4 ms refresh cycle time
FAST PAGE MODE
Operating modes: Read, Write,
Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer
Power Supply Voltage 5 V
Packages PDIP16 (300 mil)
SOJ20/26 (300 mil)
Operating temperature range
0 to 70 °C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90112
Pin Configuration
Pin Description
A8
D
W
RAS
n.c.
1
2
3
4
5
26
25
24
23
22
V
CAS
Q
Signal Name
A8
D
W
1
2
3
4
5
6
7
8
16
15
14
VSS
CAS
Q
A6
A3
A4
A5
A7
A0 - A8
D
W
RAS
UCC
USS
CAS
Q
n.c.
Signal Description
Address Inputs
Data Input
Read, Write Control
Row Address Strobe
Power Supply Voltage
Ground
Column Address Strobe
Data Output
no connected
A6
n.c.
RAS
A0
A2
PDIP
13
12
11
10
9
SOJ
A1
VCC
18
17
16
15
14
n.c.
A3
A4
A5
A7
n.c.
A0
A2
A1
VCC
9
10
11
12
13
Top View
Top View
December 12, 1997
1
UD61256
Block Diagram
CAS
Output Control
Decoder
1 out of 4
Data Output
Amplifier
4 Write-Read
Amplifier
Data
W
Write-Read Control
Q
D
Data Input Amplifier
RAS
Clock Generator
128 Kbit Array with
Sensor Amplifier
128 Kbit Array with
Sensor Amplifier
Row
Decoder
V
CC
V
SS
Column Decoder
A0
A1
A2
Address Input
A3
A4
A5
A6
A7
A8
M
U
X
A8X
A8Y
Row
Decoder
A0X to A7X
A0Y to A7Y
Operation
Address
Function
Stand-by
Read
Write
Read-Write
1st
cycle
2nd
cycle
1st
cycle
2nd
cycle
1st
cycle
2nd
cycle
RAS
H
L
L
L
L
L
L
L
L
L
L
Read L
→
H
→
L
Write L
→
H
→
L
*) Transfer of Refresh Address required
Data
C
X
D
X
X
Input Data
Input Data
X
X
Input Data
Input Data
Input Data
Input Data
X
Q
High-Z
Output
Data
High-Z
Output
Data
Output
Data
Output
Data
High-Z
High-Z
Output
Data
Output
Data
High-Z
Output
Data
High-Z
CAS
X
L
L
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
L
L
W
R
X
H
L
H
→
L
H
H
L
L
H
→
L
H
→
L
X
H
L
2
Row
Row
Row
Column
Column
Row
Row
X
Row
Row
Row
Row
Column
Column
Column
Column
Column
Column
Column
Column
Column
FPM
Read
FPM
Write
FPM
Read-Write
RAS only Refresh
HIDDEN Refresh*)
X
Input Data
December 12, 1997
UD61256
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and operating temperature range indicated below.
Absolute Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Remarks: see page 7
1)
1)
Symbol
V
CC
V
I
V
O
I
O
P
D
T
a
T
stg
Min.
-0.5
-1.0
-1.0
-50
Max.
7.0
7.0
7.0
50
1
Unit
V
V
V
mA
W
°C
°C
0
-55
70
125
Recommended Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
Remark: see page 7
1)
Symbol
V
CC
V
IL
V
IH
Min.
4.5
-1.0
2.4
Max.
5.5
0.8
5.5
Unit
V
V
V
Capacitances
Input Capacitance
A0 to A8, D
Input Capacitance
RAS, CAS, W
Output Capacitance
Conditions
Symbol
C
I1
C
I2
C
O
Min.
Max.
6
7
7
Unit
pF
pF
pF
V
CC
V
I
f
T
a
= 5.0 V
= V
SS
= 1 MHz
= 25
°C
All pins not under test must be connected with ground by capacitors.
December 12, 1997
3
UD61256
Static Characteristics
Min.
Conditions
Symbol
07
Power Supply Current
(average value of RAS-CAS cycles)
Refresh Current
(average value of RAS cycles)
FPM Current
(average value of FPM cycles)
Stand-by Current (TTL Level)
2)
Max.
Unit
08
07
70
08
60
mA
t
cW
= t
cWmin
t
cR
= t
cRmin
t
cW
= t
cWmin
t
cR
= t
cRmin
CAS = V
IH
t
cPG
= t
cPGmin
RAS = V
IL
RAS = CAS
= V
IH
RAS = CAS
= V
CC
- 0.2 V
I
OH
= -5 mA
I
OL
= 4.2 mA
V
I
= 0 V to
5.5 V
V
O
= 0 V to
5.5 V
RAS = CAS
= V
IH
I
CC1
2)
I
CC2
70
60
mA
2)
I
CC3
50
40
mA
I
CC4
2
2
mA
Stand-by Current (CMOS Level)
I
CC5
1
1
mA
Output High Voltage
Output Low Voltage
Input Leakage Current
at any input,
all other pins = 0 V
Output Leakage Current
Q = High-Z
V
OH
V
OL
I
I
2.4
2.4
0.4
0.4
10
V
V
µA
-10
-10
10
I
O
-10
-10
10
10
µA
Remarks: see page 7
4
December 12, 1997
UD61256
Symbol
Dynamic Characteristics
3)
Min.
07
08
07
Max.
Unit
08
Alt.
IEC
F
ALL CYCLES
Transition Time (Rise and Fall)
RAS Precharge Time
CAS Precharge Time
Row Address Set-up Time
Column Address Set-up Time
Row Address Hold Time
Column Address Hold Time
Column Address Hold Time ref. to RAS
Output Buffer Turn-off Delay
CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
5)
4)
t
T
t
RP
t
CP
t
ASR
t
ASC
t
RAH
t
t
3
50
10
0
0
10
15
55
0
5
15
35
0
3
60
10
0
0
10
15
60
0
5
15
40
0
50
50
ns
ns
ns
ns
ns
ns
ns
ns
t
w(RASH)
t
w(CASH)
t
su(RA-RAS)
t
su(CA-CAS)
t
h(RAS-RA)
t
h(CAS-CA)
t
h(RAS-CA)
t
v(CAS)
t
CASH-RASL
t
RAS-CA
t
CA-RASH
t
CASL-QX
t
rf
t
CAH
t
AR
t
OFF
t
CRP
t
RAD
t
RAL
t
CLZ
t
REF
20
35
20
40
ns
ns
ns
ns
ns
ms
6)
4
4
F
READ
Random Read Cycle Time
Access Time from RAS
Access Time from Column Address
Access Time from CAS
RAS Pulse Width
CAS Pulse Width
Read Command Set-up Time
Read Command Hold Time ref. to RAS
Read Command Hold Time
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
9)
9)
6)
12)
7), 8)
7), 8)
7), 8)
t
RC
t
RAC
t
AA
t
CAC
t
RAS
t
CAS
t
RCS
t
RRH
t
RCH
t
RCD
t
CSH
t
RSH
t
cR
t
a(RAS)
t
a(CA)
t
a(CAS)
t
w(RASL)
t
w(CASL)
t
su(R-CAS)
t
h(RAS-R)
t
h(CAS-R)
t
RASL-CASL
t
RASL-CASH
t
CASL-RASH
130
150
70
35
20
80
40
20
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
60
ns
ns
ns
70
20
0
0
0
20
70
20
80
20
0
0
0
20
80
20
10000
10000
F
WRITE
Random Write Cycle Time
RAS Pulse Width
CAS Pulse Width
Write Command Pulse Width
Remarks: see page 7
12)
t
RC
t
RAS
t
CAS
t
WP
t
cW
t
w(RASL)
t
w(CASL)
t
w(W)
130
70
20
15
150
80
20
15
10000
10000
10000
10000
ns
ns
ns
ns
December 12, 1997
5
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