K3P6V1000B-TC
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
FEATURES
•
Switchable organization
4,194,304 x 8(byte mode)
2,097,152 x 16(word mode)
•
Fast access time
Random Access Time : 100ns(Max.)
Page Access Time
: 30ns(Max.)
•
8 words/ 16 bytes page access
•
Supply voltage : single +3.3V
•
Current consumption
Operating : 60mA(Max.)
Standby : 30µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. K3P6V1000B-TC : 44-TSOP2-400
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P6V1000B-TC is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 4,194,304x8 bit(byte mode) or as
2,097,152x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words(or 16 bytes) of data to read fast in the same
page, CE and A
3
~ A
20
should not be changed.
This device operates with a 3.3V power supply, and all inputs
and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P6V1000B-TC is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
A
20
.
.
.
.
.
.
.
.
A
3
A
0~
A
2
A
-1
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(2,097,152x16/
4,194,304x8)
PIN CONFIGURATION
N.C
A
18
A
17
A
7
A
6
A
5
1
2
3
4
5
6
7
8
9
11
44 A
20
43 A
19
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
A
4
A
3
A
2
A
0
A
1
10
TSOP2
34 A
16
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
CE 12
V
SS
13
OE 14
Q
0
15
16
17
18
19
20
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
Q
8
Q
1
Q
9
Q
2
Q
10
Pin Name
A
0
- A
2
A
3
- A
20
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power (3.3V)
Ground
No Connection
Q
3
21
Q
11
22
K3P6V1000B-TC
K3P6V1000B-TC
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Symbol
V
IN
T
BIAS
T
STG
Rating
-0.3 to +4.5
-10 to +85
-55 to +150
CMOS MASK ROM
Unit
V
°C
°C
Remark
-
-
-
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS,
T
A
=0 to 70°C)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400µA
I
OL
=2.1mA
Test Conditions
Min
-
Max
60
500
30
-
-
2.0
-0.3
2.4
-
10
10
V
CC
+0.3
0.6
-
0.4
Unit
mA
µA
µA
µA
µA
V
V
V
V
Cycle=5MHz, all outputs open
CE=OE=V
IL
, V
IN
=0.45V to 2.4V (AC Test Condition)
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
L
OE
X
H
L
BHE
X
X
H
L
Q
15
/A
-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operting
Data
High-Z
High-Z
Q
0
~Q
15
: Dout
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
12
12
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
K3P6V1000B-TC
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
CMOS MASK ROM
AC CHARACTERISTICS
(T
A
=0°C to +70°C, V
CC
=3.3V±0.3V, unless otherwise noted.)
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and C
L
=100pF
READ CYCLE
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
Symbol
t
RC
t
ACE
t
AA
t
PA
t
OE
t
DF
t
OH
0
K3P6V1000B-TC(E)10
Min
100
100
100
30
30
20
0
Max
K3P6V1000B-TC(E)12
Min
120
120
120
50
50
20
0
Max
K3P6V1000B-TC(E)15
Min
150
150
150
70
70
30
Max
Unit
ns
ns
ns
ns
ns
ns
ns
NOTE
: Page Address is determined as below.
Word mode(BHE=V
IH
) ; A
0
, A
1
, A
2
Byte mode(BHE=V
IL
) ; A
-1
, A
0
, A
1
, A
2
K3P6V1000B-TC
TIMING DIAGRAM
READ
ADD
A
0
~A
20
A
-1(*1)
t
ACE
CE
t
OE
OE
t
OH
D
OUT
D
0
~D
7
D
8
~D
15(*2)
VALID DATA
t
AA
CMOS MASK ROM
ADD1
t
RC
ADD2
t
DF(*3)
VALID DATA
PAGE READ
≈
CE
t
DF(*3)
OE
ADD
A
0,
A
1,
A
2
A
-1(*1)
t
AA
D
OUT
D
0
~D
7
D
8
~D
15(*2)
1 st
t
PA
VALID DATA
2 nd
3 rd
≈
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
≈
≈
≈
≈
ADD
A
3
~A
20
≈
≈
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