Product Obsolete or Under Obsolescence
0
R
XC3000 Series
Field Programmable Gate Arrays
(XC3000A/L, XC3100A/L)
0
7*
November 9, 1998 (Version 3.1)
Product Description
•
Complete Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Features
•
Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
package
- Avoids the NRE, time delay, and risk of conventional
masked gate arrays
High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 7 to 1.5 ns
- System clock speeds over 85 MHz
- Low quiescent and active power consumption
Flexible FPGA architecture
- Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
Extensive packaging options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
array packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
Device
XC3020A, 3020L, 3120A
XC3030A, 3030L, 3130A
XC3042A, 3042L, 3142A, 3142L
XC3064A, 3064L, 3164A
XC3090A, 3090L, 3190A, 3190L
XC3195A
Max Logic
Gates
1,500
2,000
3,000
4,500
6,000
7,500
Typical Gate
CLBs
Range
1,000 - 1,500
64
1,500 - 2,000
2,000 - 3,000
3,500 - 4,500
5,000 - 6,000
6,500 - 7,500
100
144
224
320
484
•
Additional XC3100A Features
•
Ultra-high-speed FPGA family with six members
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
High-end additional family member in the 22 X 22 CLB
array-size XC3195A device
8 mA output sink current and 8 mA source current
Maximum power-down and quiescent current is 5 mA
100% architecture and pin-out compatible with other
XC3000 families
Software and bitstream compatible with the XC3000,
XC3000A, and XC3000L families
•
•
•
•
•
•
•
7
XC3100A combines the features of the XC3000A and
XC3100 families:
•
•
•
•
Additional interconnect resources for TBUFs and CE
inputs
Error checking of the configuration bitstream
Soft startup holds all outputs slew-rate limited during
initial power-up
More advanced CMOS process
•
•
Low-Voltage Versions Available
•
•
•
Low-voltage devices function at 3.0 - 3.6 V
XC3000L - Low-voltage versions of XC3000A devices
XC3100L - Low-voltage versions of XC3100A devices
•
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
User I/Os
Flip-Flops
Max
64
256
80
96
120
144
176
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
32
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
November 9, 1998 (Version 3.1)
7-3
Product Obsolete or Under Obsolescence
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XC3000 Series Field Programmable Gate Arrays
Introduction
XC3000-Series Field Programmable Gate Arrays (FPGAs)
provide a group of high-performance, high-density, digital
integrated circuits. Their regular, extendable, flexible,
user-programmable array architecture is composed of a
configuration program store plus three types of config-
urable elements: a perimeter of I/O Blocks (IOBs), a core
array of Configurable Logic Bocks (CLBs) and resources
for interconnection. The general structure of an FPGA is
shown in
Figure 2.
The development system provides
schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation
are available as design verification alternatives. The design
editor is used for interactive design optimization, and to
compile the data pattern that represents the configuration
program.
The FPGA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial Configu-
ration PROMs provide a very simple serial configuration
program storage in a one-time programmable package.
The XC3000 Field Programmable Gate Array families pro-
vide a variety of logic capacities, package styles, tempera-
ture ranges and speed grades.
Here is a simple overview of those XC3000 products cur-
rently emphasized:
•
XC3000A Family
— The XC3000A is an enhanced
version of the basic XC3000 family, featuring additional
interconnect resources and other user-friendly
enhancements.
XC3000L Family
— The XC3000L is identical in
architecture and features to the XC3000A family, but
operates at a nominal supply voltage of 3.3 V. The
XC3000L is the right solution for battery-operated and
low-power applications.
XC3100A Family
— The XC3100A is a
performance-optimized relative of the XC3000A family.
While both families are bitstream and footprint
compatible, the XC3100A family extends toggle rates to
370 MHz and in-system performance to over 80 MHz.
The XC3100A family also offers one additional array
size, the XC3195A.
XC3100L Family
— The XC3100L is identical in
architectures and features to the XC3100A family, but
operates at a nominal supply voltage of 3.3V.
•
•
•
Figure 1
illustrates the relationships between the families.
Compared to the original XC3000 family, XC3000A offers
additional functionality and increased speed. The XC3000L
family offers the same additional functionality, but reduced
speed due to its lower supply voltage of 3.3 V. The
XC3100A family offers substantially higher speed and
higher density with the XC3195A.
New XC3000 Series Compared to Original
XC3000 Family
For readers already familiar with the original XC3000 family
of FPGAs, the major new features in the XC3000A,
XC3000L, XC3100A, and XC3100L families are listed in
this section.
All of these new families are upward-compatible extensions
of the original XC3000 FPGA architecture. Any bitstream
used to configure an XC3000 device will configure the cor-
responding XC3000A, XC3000L, XC3100A, or XC3100L
device exactly the same way.
The XC3100A and XC3100L FPGA architectures are
upward-compatible extensions of the XC3000A and
XC3000L architectures. Any bitstream used to configure an
XC3000A or XC3000L device will configure the corre-
sponding XC3100A or XC3100L device exactly the same
way.
XC3000 Series Overview
There are now four distinct family groupings within the
XC3000 Series of FPGA devices:
•
•
•
•
XC3000A Family
XC3000L Family
XC3100A Family
XC3100L Family
All four families share a common architecture, develop-
ment software, design and programming methodology, and
also common package pin-outs. An extensive Product
Description covers these common aspects.
Detailed parametric information for the XC3000A,
XC3000L, XC3100A, and XC3100L product families is then
provided. (The XC3000 and XC3100 families are not rec-
ommended for new designs.)
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November 9, 1998 (Version 3.1)
Product Obsolete or Under Obsolescence
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XC3000 Series Field Programmable Gate Arrays
Improvements in the XC3000A and XC3000L
Families
The XC3000A and XC3000L families offer the following
enhancements over the popular XC3000 family:
The XC3000A and XC3000L families have additional inter-
connect resources to drive the I-inputs of TBUFs driving
horizontal Longlines. The CLB Clock Enable input can be
driven from a second vertical Longline. These two additions
result in more efficient and faster designs when horizontal
Longlines are used for data bussing.
During configuration, the XC3000A and XC3000L devices
check the bit-stream format for stop bits in the appropriate
positions. Any error terminates the configuration and pulls
INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
out-puts are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000 fam-
ily, determined by the individual configuration option.
195A
(XC3
)
Functio
nality
XC310
00
0
XC310XC31
L
0A
XC300
XC300
0L
0A
Speed
city
Capa
Gate
X7068
Figure 1: XC3000 FPGA Families
Improvements in the XC3100A and XC3100L
Families
Based on a more advanced CMOS process, the XC3100A
and XC3100L families are architecturally-identical, perfor-
mance-optimized relatives of the XC3000A and XC3000L
families. While all families are footprint compatible, the
XC3100A family extends achievable system performance
beyond 85 MHz.
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November 9, 1998 (Version 3.1)
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Product Obsolete or Under Obsolescence
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XC3000 Series Field Programmable Gate Arrays
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Con-
figurable Logic Blocks (CLBs) performs user-specified logic
functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks, analo-
gous to printed circuit board traces connecting MSI/SSI
packages.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by pro-
gram-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the device at power-up and may be reloaded
on command. The FPGA includes logic and control signals
to implement automatic or passive configuration. Program
data may be either bit serial or byte parallel. The develop-
ment system generates the configuration program bit-
stream used to configure the device. The memory loading
process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory
in the Field Programmable Gate Array has been designed
specifically for high reliability and noise immunity. Integrity
of the device configuration memory based on this design is
assured even under adverse conditions. As shown in
Figure 3,
the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading
cell data. The cell is only written during configuration and
only read during readback. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
PWR
DN
P9
P8
P7
P6
P5
P4
P3
P2
GND
I/O Blocks
P11
3-State Buffers With Access
to Horizontal Long Lines
Configurable Logic
Blocks
TCL
KIN
AA
P12
AB
AC
AD
Interconnect Area
P13
BA
U61
BB
Configuration Memory
X3241
Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
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November 9, 1998 (Version 3.1)
Frame Pointer
Product Obsolete or Under Obsolescence
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XC3000 Series Field Programmable Gate Arrays
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
Configuration
Control
Q
Read or
Write
Data
Q
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in
Figure 4,
provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
Vcc
The memory cell outputs Q and Q use ground and V
CC
lev-
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
PROGRAM-CONTROLLED MEMORY CELLS
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
7
3- STATE
(OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP
FLOP
OUTPUT
BUFFER
I/O PAD
R
DIRECT IN
REGISTERED IN
I
Q
Q
D
FLIP
FLOP
or
LATCH
R
OK
IK
(GLOBAL RESET)
TTL or
CMOS
INPUT
THRESHOLD
CK1
CK2
PROGRAM
CONTROLLED
MULTIPLEXER
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
November 9, 1998 (Version 3.1)
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