BX80528KL140GA datasheet, PDF - EEWORLD Datasheet

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BX80528KL140GA: DescriptionMicroprocessor, 32-Bit, 1400MHz, CMOS, CPGA603, PGA-603; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，116 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80528KL140GA Overview

Microprocessor, 32-Bit, 1400MHz, CMOS, CPGA603, PGA-603

BX80528KL140GA Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	PGA
package instruction	SPGA, PGA603,25X31,50
Contacts	603
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P603
length	53.34 mm
low power mode	YES
Number of terminals	603
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Encapsulate equivalent code	PGA603,25X31,50
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
power supply	1.6 V
Certification status	Not Qualified
Maximum seat height	5.53 mm
speed	1400 MHz
Maximum slew rate	41700 mA
Maximum supply voltage	1.7 V
Minimum supply voltage	1.55 V
Nominal supply voltage	1.6 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	53.34 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

BX80528KL140GA Preview

Intel

Xeon

™

Processor MP

at 1.40 GHz, 1.50 GHz and 1.60 GHz

Datasheet

Product Features

Available at 1.40, 1.50 and 1.60GHz

4-way and greater multi-processing server

support

Binary compatible with applications

running on Intel IA-32 architecture

processors

Hyper-Threading Technology enabling

multi-threading server software to execute

threads in parallel on each processor

400 MHz system bus

— Bandwidth up to 3.2 Gbytes/sec

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

Enables system support of up to 64 GB of

physical memory

Advance Dynamic Execution

— Very deep out-of-order execution

— Enhanced branch prediction

Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency

from main execution loops

— Includes 8 KB Level 1 data cache

Intel

NetBurst™ micro-architecture

256 KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache) with 8-way

associativity and Error Correcting Code

(ECC)

512 KB or 1 MB of Integrated Level 3

Cache (on-die, full speed Level 3 Cache)

with Error Correcting Code (ECC) provides

faster access to large server instruction and

data sets

144 new Streaming SIMD Extensions 2

(SSE2) instructions

Enhanced floating point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

Power Management capabilities

— System Management mode

— Multiple low-power states

Advanced System Management Features

— Processor Information ROM (PIROM)

— System Management Bus (SMBus)

— OEM Scratch EEPROM

— Machine Check Architecture (MCA)

The Intel

Xeon™ processor MP is designed for high-performance enterprise and e-Business

server applications. Based on the Intel

NetBurst™ micro-architecture, it is binary compatible

with previous Intel IA-32 Architecture processors and introduces Hyper-Threading technology

to multi-processing server platforms. The Intel Xeon processor MP is scalable to four of more

processors in a multiprocessor system providing exceptional performance for enterprise server

applications running on advanced operating systems such as Windows 2000 Server*, Linux*,

Netware* and UNIX*. The Intel Xeon processor MP extends the power of the Intel

Pentium

III

Xeon™ processor with new features designed to make this processor the right choice for

powerful enterprise server, and mission-critical applications. Advanced features simplify system

management and meet the needs of a robust IT environment, resulting in maximized system up

time, convenient system management, and optimal configuration.

Order Number: 290740-002

March 2002

Information in this document is provided in connection with Intel

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its subsidiaries in the

United States and other countries.

* Other names and brands may be claimed as the property of others.

Datasheet

Contents

1.0

Introduction

...............................................................................................................11

1.1

1.2

1.3

Terminology.........................................................................................................12

1.1.1 Processor Packaging Terminology.........................................................12

References ..........................................................................................................13

State of Data .......................................................................................................14

System Bus and GTLREF ...................................................................................15

Power and Ground Pins ......................................................................................15

Decoupling Guidelines ........................................................................................15

2.3.1 VCC Decoupling .....................................................................................16

2.3.2 System Bus AGTL+ Decoupling.............................................................16

System Bus Clock (BCLK[1:0]) and Processor Clocking ....................................16

2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................17

2.4.2 System Bus to Core Frequency Ratios ..................................................18

2.4.3 Mixing Processors ..................................................................................19

Voltage Identification ..........................................................................................19

2.5.1 Mixing Processors of Different Voltages ................................................20

Reserved Or Unused Pins...................................................................................21

System Bus Signal Groups .................................................................................21

Asynchronous GTL+ Signals...............................................................................23

Test Access Port (TAP) Connection....................................................................23

Maximum Ratings................................................................................................23

Processor DC Specifications...............................................................................24

AGTL+ System Bus Specifications .....................................................................28

System Bus AC Specifications ............................................................................29

Processor AC Timing Waveforms .......................................................................34

System Bus Clock (BCLK) Signal Quality Specifications and Measurement

Guidelines ...........................................................................................................41

System Bus Signal Quality Specifications and Measurement Guidelines...........42

3.2.1 Ringback Guidelines ..............................................................................42

3.2.2 Overshoot/Undershoot Guidelines .........................................................45

3.2.3 Overshoot/Undershoot Magnitude .........................................................45

3.2.4 Overshoot/Undershoot Pulse Duration...................................................46

3.2.5 Activity Factor .........................................................................................46

3.2.6 Reading Overshoot/Undershoot Specification Tables............................46

3.2.7 Determining if a System Meets the Overshoot/Undershoot

Specifications .........................................................................................47

Processor Mechanical Specifications..................................................................53

Package Load Specifications ..............................................................................56

Processor Insertion Specifications ......................................................................57

Processor Mass Specifications ...........................................................................57

Processor Materials.............................................................................................57

2.0

Electrical Specifications

........................................................................................15

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

3.0

System Bus Signal Quality Specifications

....................................................41

3.1

3.2

4.0

Mechanical Specifications

....................................................................................51

4.1

4.2

4.3

4.4

4.5

Datasheet

Contents

4.6

4.7

Processor Markings ............................................................................................ 57

Processor Pin-Out Diagrams .............................................................................. 59

Processor Pin Assignments ................................................................................ 61

5.1.1 Pin Listing by Pin Name ......................................................................... 61

5.1.2 Pin Listing by Pin Number ...................................................................... 70

Signal Definitions ................................................................................................ 79

Thermal Specifications........................................................................................ 89

Thermal Analysis................................................................................................. 90

6.2.1 Measurements For Thermal Specifications............................................ 90

6.2.1.1 Processor Case Temperature Measurement ............................ 90

Power-On Configuration Options ........................................................................ 91

Clock Control and Low Power States.................................................................. 91

7.2.1 Normal State—State 1 ........................................................................... 91

7.2.2 AutoHALT Powerdown State—State 2 .................................................. 92

7.2.3 Stop-Grant State—State 3 ..................................................................... 92

7.2.4 HALT/Grant Snoop State—State 4 ........................................................ 93

7.2.5 Sleep State—State 5.............................................................................. 93

7.2.6 Bus Response During Low Power States .............................................. 94

Thermal Monitor .................................................................................................. 94

7.3.1 Thermal Diode........................................................................................ 95

System Management Bus (SMBus) Interface ..................................................... 95

7.4.1 Processor Information ROM (PIR) ......................................................... 96

7.4.2 Scratch EEPROM .................................................................................. 98

7.4.3 PIR and Scratch EEPROM Supported SMBus Transactions................. 99

7.4.4 SMBus Thermal Sensor ......................................................................... 99

7.4.5 Thermal Sensor Supported SMBus Transactions ................................ 100

7.4.6 SMBus Thermal Sensor Registers ....................................................... 102

7.4.6.1 Thermal Reference Registers ................................................. 102

7.4.6.2 Thermal Limit Registers .......................................................... 102

7.4.6.3 Status Register........................................................................ 102

7.4.6.4 Configuration Register............................................................. 103

7.4.6.5 Conversion Rate Registers ..................................................... 104

7.4.7 SMBus Thermal Sensor Alert Interrupt ................................................ 104

7.4.8 SMBus Device Addressing................................................................... 104

Introduction ....................................................................................................... 107

Mechanical Specifications................................................................................. 108

8.2.1 Boxed Processor Heatsink Dimensions ............................................... 108

8.2.2 Boxed Processor Heatsink Weight....................................................... 108

8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports......... 108

Boxed Processor Requirements ....................................................................... 110

8.3.1 Intel® Xeon™ Processor MP ............................................................... 110

Thermal Specifications...................................................................................... 110

8.4.1 Boxed Processor Cooling Requirements ............................................. 110

5.0

Pin Listing and Signal Definitions

..................................................................... 61

5.1

5.2

6.0

Thermal Specifications

.......................................................................................... 88

6.1

6.2

7.0

Features

....................................................................................................................... 91

7.1

7.2

7.3

7.4

8.0

Boxed Processor Specifications

..................................................................... 107

8.1

8.2

8.3

8.4

Datasheet

Contents

9.0

Debug Tools Specifications

...............................................................................113

9.1

9.2

9.3

Debug Port System Requirements....................................................................113

Target System Implementation .........................................................................114

9.2.1 System Implementation........................................................................114

Logic Analyzer Interface (LAI) ..........................................................................114

9.3.1 Mechanical Considerations ..................................................................114

9.3.2 Electrical Considerations......................................................................114

Processor Core Frequency Determination ........................................................115

10.0

Appendix A

...............................................................................................................115

10.1

Datasheet

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BX80528KL140GA Related Products

	BX80528KL140GA	YF80528KC021512/SL5G2
Description	Microprocessor, 32-Bit, 1400MHz, CMOS, CPGA603, PGA-603	RISC Microprocessor, 32-Bit, 1500MHz, CMOS, PPGA603
package instruction	SPGA, PGA603,25X31,50	SPGA, PGA603,25X31,50
Reach Compliance Code	unknown	unknown
bit size	32	32
JESD-30 code	S-CPGA-P603	R-PPGA-P603
Number of terminals	603	603
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY
encapsulated code	SPGA	SPGA
Encapsulate equivalent code	PGA603,25X31,50	PGA603,25X31,50
Package shape	SQUARE	RECTANGULAR
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
power supply	1.6 V	1.6 V
Certification status	Not Qualified	Not Qualified
speed	1400 MHz	1500 MHz
Maximum slew rate	41700 mA	50000 mA
Nominal supply voltage	1.6 V	1.6 V
surface mount	NO	NO
technology	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR, RISC

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