BX80532KC2200D datasheet, PDF - EEWORLD Datasheet

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BX80532KC2200D: DescriptionMicroprocessor, 32-Bit, 2200MHz, CMOS, CPGA603, PGA-603; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，129 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80532KC2200D Overview

Microprocessor, 32-Bit, 2200MHz, CMOS, CPGA603, PGA-603

BX80532KC2200D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	PGA
package instruction	SPGA, PGA603,25X31,50
Contacts	603
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P603
JESD-609 code	e0
length	53.34 mm
low power mode	YES
Number of terminals	603
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Encapsulate equivalent code	PGA603,25X31,50
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.4,3.3 V
Certification status	Not Qualified
Maximum seat height	5.45 mm
speed	2200 MHz
Maximum slew rate	48100 mA
Maximum supply voltage	1.46 V
Minimum supply voltage	1.352 V
surface mount	NO
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	53.34 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Intel

Xeon

™

Processor with 512-KB L2 Cache

at 1.80 GHz to 3 GHz

Datasheet

Product Features

•

Available at 1.80, 2, 2.20, 2.40, 2.60, 2.80, and

3 GHz

Dual processing server/workstation support

Binary compatible with applications running on

previous members of Intel’s IA32

microprocessor line

Intel

NetBurst™ micro-architecture

Hyper-Threading Technology

— Hardware support for multithreaded

applications

400 MHz Front Side Bus

— Bandwidth up to 3.2 GB/second

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

Hyper Pipelined Technology

Advance Dynamic Execution

— Very deep out-of-order execution

— Enhanced branch prediction

Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency from

main execution loops

— Includes 8 KB Level 1 data cache

•

512 KB Advanced Transfer L2 Cache (on-die,

full speed Level 2 cache) with 8-way

associativity and Error Correcting Code (ECC)

Enables system support of up to 64 GB of

physical memory

Streaming SIMD Extensions 2 (SSE2)

— 144 new instructions for double-precision

floating point operations, media/video

streaming, and secure transactions

Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D

performance

Power Management capabilities

— System Management mode

— Multiple low-power states

Advanced System Management Features

— System Management Bus

— Processor Information ROM (PIROM)

— OEM Scratch EEPROM

— Thermal Monitor

— Machine Check Architecture (MCA)

The Intel

Xeon™ processor with 512 KB L2 cache is designed for high-performance dual-

processor workstation and server applications. Based on the Intel

NetBurst™ micro-

architecture and the new Hyper-Threading Technology, it is binary compatible with previous

Intel Architecture (IA-32) processors. The Intel Xeon processor with 512 KB L2 cache is

scalable to two processors in a multiprocessor system providing exceptional performance for

applications running on advanced operating systems such as Windows XP*, Windows* 2000,

Linux*, and UNIX*. The Intel Xeon processor with 512 KB L2 cache delivers compute power at

unparalleled value and flexibility for powerful workstations, internet infrastructure, and

departmental server applications. The Intel

NetBurst™ micro-architecture and Hyper-

Threading Technology deliver outstanding performance and headroom for peak internet server

workloads, resulting in faster response times, support for more users, and improved scalability.

Order Number: 298642-006

March

2003

Contents

1.0

Introduction....................................................................................................................................11

1.1

Terminology ......................................................................................................................12

1.2

State of Data.....................................................................................................................13

1.3

References .......................................................................................................................14

Electrical Specifications .................................................................................................................15

2.1

Front Side Bus and GTLREF............................................................................................15

2.2

Power and Ground Pins ...................................................................................................15

2.3

Decoupling Guidelines......................................................................................................15

2.4

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking .............................................16

2.5

PLL Filter ..........................................................................................................................17

2.6

Voltage Identification .......................................................................................................20

2.7

Reserved Or Unused Pins ................................................................................................22

2.8

Front Side Bus Signal Groups ..........................................................................................22

2.9

Asynchronous GTL+ Signals ............................................................................................24

2.10

Maximum Ratings .............................................................................................................24

2.11

Processor DC Specifications ............................................................................................25

2.12

AGTL+ Front Side Bus Specifications ..............................................................................31

2.13

Front Side Bus AC Specifications.....................................................................................32

2.14

Processor AC Timing Waveforms.....................................................................................36

Front Side Bus Signal Quality Specifications ................................................................................45

3.1

Front Side Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines.

..........................................................................................................................................45

3.2

Front Side Bus Signal Quality Specifications and Measurement Guidelines....................46

3.3

Front Side Bus Signal Quality Specifications and Measurement Guidelines....................50

Mechanical Specifications .............................................................................................................57

4.1

Mechanical Specifications ................................................................................................58

4.2

Processor Package Load Specifications ..........................................................................62

4.3

Insertion Specifications.....................................................................................................63

4.4

Mass Specifications ..........................................................................................................63

4.5

Materials ...........................................................................................................................63

4.6

Markings ...........................................................................................................................64

4.7

Pin-Out Diagram ...............................................................................................................65

Pin Listing and Signal Definitions ..................................................................................................67

5.1

Processor Pin Assignments..............................................................................................67

5.2

Signal Definitions .............................................................................................................84

Thermal Specifications ..................................................................................................................95

6.1

Thermal Specifications .....................................................................................................96

6.2

Measurements for Thermal Specifications .......................................................................98

Features ........................................................................................................................................99

7.1

Power-On Configuration Options......................................................................................99

7.2

Clock Control and Low Power States ...............................................................................99

7.3

Thermal Monitor .............................................................................................................102

7.4

System Management Bus (SMBus) Interface.................................................................103

Boxed Processor Specifications ..................................................................................................115

8.1

Introduction .....................................................................................................................115

8.2

Mechanical Specifications ..............................................................................................116

8.3

1U Rack Mount Server Solution .....................................................................................125

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Datasheet

Contents

Figures

Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................................................18

Phase Lock Loop (PLL) Filter Requirements ............................................................................19

Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)........................27

Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID = 1.525V)...................28

Electrical Test Circuit.................................................................................................................37

TCK Clock Waveform................................................................................................................37

Differential Clock Waveform......................................................................................................38

Differential Clock Crosspoint Specification................................................................................38

Front Side Bus Common Clock Valid Delay Timing Waveform.................................................39

Front Side Bus Source Synchronous 2X (Address) Timing Waveform .....................................39

Front Side Bus Source Synchronous 4X (Data) Timing Waveform...........................................40

Front Side Bus Reset and Configuration Timing Waveform......................................................41

Power-On Reset and Configuration Timing Waveform .............................................................41

TAP Valid Delay Timing Waveform ...........................................................................................42

Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform .........................42

THERMTRIP# to VCC Timing ...................................................................................................42

SMBus Timing Waveform..........................................................................................................43

SMBus Valid Delay Timing Waveform ......................................................................................43

Example 3.3 VDC/SM_VCC Sequencing..................................................................................44

BCLK[1:0] Signal Integrity Waveform........................................................................................46

Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+

Buffers ......................................................................................................................................47

High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+

Buffers ......................................................................................................................................48

Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers ........48

High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers .49

Maximum Acceptable Overshoot/Undershoot Waveform .........................................................55

INT-mPGA Processor Package Assembly Drawing (Includes Socket) .....................................57

INT-mPGA Processor Package Top View: Component Placement Detail................................58

INT-mPGA Processor Package Drawing ..................................................................................59

INT-mPGA Processor Package Top View: Component Height Keep-in ...................................60

INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in ................60

INT-mPGA Processor Package: Pin Detail ...............................................................................61

IHS Flatness and Tilt Drawing...................................................................................................62

Processor Top-Side Markings ...................................................................................................64

Processor Bottom-Side Markings..............................................................................................64

Processor Pin Out Diagram: Top View......................................................................................65

Processor Pin Out Diagram: Bottom View ................................................................................66

Processor with Thermal and Mechanical Components - Exploded View ..................................95

Processor Thermal Design Power vs Electrical Projections for VID = 1.500V ..........................96

Processor Thermal Design Power vs Electrical Projections for VID = 1.525V ..........................97

Thermal Measurement Point for Processor TCASE..................................................................98

Stop Clock State Machine .......................................................................................................100

Logical Schematic of SMBus Circuitry ....................................................................................104

Mechanical Representation of the Boxed Processor Passive Heatsink for 3 GHz processors

................................................................................................................................................115

Datasheet

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