FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11045-1E
MEMORY
CMOS
4
×
1 M
×
16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F641642C-102/-103/-102L/-103L
CMOS 4-Bank
×
1,048,576-Word
×
16 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB81F641642C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 16-bit format. The MB81F641642C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F641642C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB81F641642C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
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PRODUCT LINE & FEATURES
Parameter
CL - t
RCD -
t
RP
Clock Frequency
Burst Mode Cycle Time
Access Time From Clock (CL = 3)
Operating Current (2 banks active)
Power Down Mode Current (I
CC2P
)
Self Refresh Current (I
CC6
)
MB81F641642C
-102
-102L
-103
-103L
2 - 2 - 2 clk min.
100 MHz max.
10 ns min.
6 ns max.
105 mA max.
2 mA max.
1 mA max.
1 mA max.
500
µA
max.
3 - 2 - 2 clk min.
100 MHz max.
10 ns min.
6 ns max.
105 mA max.
2 mA max.
1 mA max.
1 mA max.
500
µA
max.
•
•
•
•
•
Single +3.3 V Supply ±0.3 V tolerance
LVTTL compatible I/O
4 K refresh cycles every 65.6 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
• Standard and low power versions
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 16
µs)
• CKE power down mode
• Output Enable and Input Data Mask
MB81F641642C-102/-103/-102L/-103L
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PACKAGE
Plastic TSOP(II) Package
Marking side
(FPT-54P-M02)
(Normal Bend)
Package and Ordering Information
– 54-pin plastic (400 mil) TSOP-II, order as MB81F641642C-×××FN (Std power),
MB81F641642C-×××LFN (Low power), MB81F641642C-×××EFN (Extra power)
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MB81F641642C-102/-103/-102L/-103L
s
PIN ASSIGNMENTS AND DESCRIPTIONS
54-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-54P-M02>
V
CC
DQ
0
V
CCQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
CCQ
DQ
5
DQ
6
V
SSQ
DQ
7
V
CC
DQML
WE
CAS
RAS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
CCQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
CCQ
DQ
8
V
SS
N.C.
DQMU
CLK
CKE
N.C.
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
(Marking side)
Pin Number
1, 3, 9, 14, 27, 43, 49
2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47,
48, 50, 51, 53
6, 12, 28, 41, 46, 52, 54
36, 40
16
17
18
19
20, 21
22
22, 23, 24, 25, 26, 29, 30, 31, 32, 33,
34, 35
37
38
15, 39
Symbol
V
CC
, V
CCQ
DQ
0
to DQ
15
V
SS
, V
SSQ
*
N.C.
WE
CAS
RAS
CS
A
13
(BA
0
), A
12
(BA
1
)
AP
A
0
to A
11
CKE
CLK
DQML, DQMU
Supply Voltage
Data I/O
Ground
No Connection
Write Enable
Function
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
Address Input
Clock Enable
Clock Input
Input Mask/Output Enable
• Row: A
0
to A
11
• Column: A
0
to A
7
* : These pins are connected internally in the chip.
3
MB81F641642C-102/-103/-102L/-103L
s
BLOCK DIAGRAM
Fig. 1 – MB81F641642C BLOCK DIAGRAM
CLK
To each block
CLOCK
BUFFER
CKE
BANK-3
BANK-2
BANK-1
BANK-0
RAS
CS
CONTROL
SIGNAL
LATCH
COMMAND
DECODER
CAS
RAS
CAS
WE
WE
MODE
REGISTER
A
0
to A
11
,
AP
DRAM
CORE
(4,096
×
256
×
16)
ADDRESS
BUFFER/
REGISTER
A
12
, A
13
ROW
ADDR.
DQML
DQMU
COLUMN
ADDRESS
COUNTER
I/O DATA
BUFFER/
REGISTER
COL.
ADDR.
I/O
V
CC
V
CCQ
V
SS
/V
SSQ
DQ
0
to
DQ
15
4
MB81F641642C-102/-103/-102L/-103L
s
FUNCTIONAL TRUTH TABLE Note 1
COMMAND TRUTH TABLE
Function
Device Deselect
No Operation
Burst Stop
Read
Read with Auto-precharge
Write
Write with Auto-precharge
Bank Active (RAS)
Precharge Single Bank
Precharge All Banks
Mode Register Set
Notes:
*1.
*2.
*3.
*4.
*5.
*6.
*8, 9
*6
Notes 2, 3, and 4
CKE
CS
n-1
*5
*5
DESL
NOP
BST
READ
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
X
H
L
H
H
L
L
H
L
L
L
RAS
CAS
WE
A
13
,
A
12
(BA)
X
X
X
V
V
V
V
V
V
X
X
A
10
(AP)
X
X
X
L
H
L
H
V
L
H
X
A
11
X
X
X
X
X
X
X
V
X
X
X
A
9
to
A
0
X
X
X
V
V
V
V
V
X
X
V
Notes Symbol
*6 READA
*6
WRIT
*6 WRITA
*7
ACTV
PRE
PALL
MRS
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
All commands assumes no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
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