M2V56S20ATP-5UL datasheet, PDF

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M2V56S20ATP-5UL: DescriptionSynchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54; Categorystorage storage; File Size420KB，51 Pages; ManufacturerMitsubishi; Websitehttp://www.mitsubishielectric.com/semiconductors/

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M2V56S20ATP-5UL Overview

Synchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54

M2V56S20ATP-5UL Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Mitsubishi
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.17 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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MITSUBISHI LSIs

SDRAM (Rev.1.31)

Single Data Rate

Apr. '02

M2V56S20/ 30/ 40 ATP

M2V56S20/ 30/ 40 AKT

256M Synchronous DRAM

Contents are subject to change without notice.

DESCRIPTION

M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit,

M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit,

M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit,

synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of

CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),

and are suitable for main memory or graphic memory in computer systems.

FEATURES

Max. Frequency Max. Frequency

@CL2

@CL3

M2V56S20/30/40ATP/KT-5/-5L/-5UL

M2V56S20/30/40ATP/KT-6/-6L/-6UL

M2V56S20/30/40ATP/KT-7/-7L/-7UL

133MHz

100MHz

133MHz

100MHz

Standard

PC133 (CL2)

PC133 (CL3)

PC100 (CL2)

Note: The –5L/-6L/-7L is Self-refresh low power.

The –5LU/-6UL/-7UL is Self-refresh ultra low power.

- Single 3.3v + 0.3V power supply

- Max. Clock frequency -5:PC133<2-2-2> / -6:PC133<3-3-3> / -7:PC100<2-2-2>

- Fully Synchronous operation referenced to clock rising edge

- Single Data Rate

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/full page (programmable)

- Burst type- sequential / interleave (programmable)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- LVTTL Interface

- Both 54-pin TSOP Package and 64-pin Small TSOP Package

M2V56S*0ATP: 0.8mm lead pitch 54-pin TSOP Package

M2V56S*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package (sTSOP)

- Low Power for the Self Refresh Current ICC6 : 2.0mA (–5L,-6L,-7L)

- Ultra Low Power for the Self Refresh Current ICC6 : 1.0mA (–5UL,-6UL,-7UL)

MITSUBISHI ELECTRIC

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