K8P6415UQB
FLASH MEMORY
64Mb B-die Page NOR Specification
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
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* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.4
June 2007
K8P6415UQB
FLASH MEMORY
Document Title
64M Bit (4M x16) Page Mode / Multi-Bank NOR Flash Memory
Revision History
Revision No. History
0.0
Initial draft
Draft Date
June 26, 2006
Remark
Target
Information
Target
Information
Target
Information
0.1
- Adding 48-FBGA Information
July 28, 2006
0.2
- Correct TSOP Pin configuration
August 4, 2006
- Correct contents of Table 9 (Boot Block/Block Addresses for Protect-
ion / Unprotection)
- Correct Chip Erase time(typ)
- Correct t
OES
(OE Setup Time) patameter at page 42
- Correct 56 Ball FBGA Top View
- Vih is changed 2.0 to 2.2V(min)
- 48FBGA (6x8mm) is added
-Accelerated Program Time is changed from 4us to 6us.
-Accelerated Quad Word Program Time is changed from 1.2us to
1.5us.
-Package Dimension Informaion is added.
-48FBGA 6x9 is transfered to 48FBGA 6x8.
-64FBGA 13x11 with 1.0mm Pitch is added.
- 56 Pin TSOP 20x14mm and 56 Ball FBGA 7x9mm are deleted.
-Change Vih Min. from Vio-0.4(2.2) to Vio-0.4(Vccx0.8)
-Change Vil Max. from 0.4(0.8) to 0.4(Vccx0.2)
-48TSOP Demension is added
- Group block protect time : 100us --> 120us
- Group block unprotect time : 1.2ms --> 3ms
In Figure 8. Block Group Protection & Unprotection Algorithms
& Block Group Protect & Unprotect Operations timing
- Package Hight is changed from 1.3
±0.10
to 1.2
±0.10.
- "#OE or #CE should be toggled in each toggle bit status read." is
added in DQ2 & DQ6 toggle bit.
- Package 'E' is added in ordering information.
- Absolute maximum ratings
All other pins value is changed -0.5 to 2.5 to -0.5 to Vcc + 0.5.
- Fast access time 55ns is deleted.
0.3
0.4
0.5
0.6
September 4, 2006 Target
Information-
Target
October 09,2006
Information
November 02,2006 Target
Information
November 13,2006 Target
Information
0.7
November 19,2006 Target
Information
January 16,2007
Target
Information
0.8
February 08,2007
1.0
1.1
1.2
February 15, 2007
April 23, 2007
1.3
June 21, 2007
1.4
June 28, 2007
2
Revision 1.4
June 2007
K8P6415UQB
FLASH MEMORY
64M Bit (4M x16) Page Mode / Multi-Bank NOR Flash Memory
FEATURES
•
Single Voltage, 2.7V to 3.6V for Read and Write operations
Voltage range of 2.7V to 3.1V valid for MCP product
•
Organization
4M x16 bit (Word mode Only)
•
Fast Read Access Time : 60ns
•
Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 20ns
•
Read While Program/Erase Operation
•
Multiple Bank architectures (4 banks)
Bank 0: 8Mbit (4Kw x 8 and 32Kw x 15)
Bank 1: 24Mbit (32Kw x 48)
Bank 2: 24Mbit (32Kw x 48)
Bank 3: 8Mbit (4Kw x 8 and 32Kw x 15)
•
OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
•
Power Consumption (typical value)
- Active Read Current : 45mA (@10MHz)
- Program/Erase Current : 17mA
- Read While Program or Read While Erase Current : 35mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Support Single & Quad word accelerate program
•
WP/ACC input pin
- Allows special protection of two outermost boot blocks at V
IL
,
regardless of block protect status
- Removes special protection of two outermost boot block at V
IH,
the two blocks return to normal block protect status
- Accelerated Quadword Program time : 1.5us
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program
•
Hardware RESET Pin
•
Command Register Operation
•
Block Protection / Unprotection
•
Supports Common Flash Memory Interface
•
Operation Temperature Rnage
- Industrial Temperature : -40°C to 85°C
- Extended Temperature : -25°C to 85°C
- Commercial Temperature : 0°C to 70°C
•
Endurance : 100,000 Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Vio options at 1.8V and 3V I/O
•
Package options
- 48 Pin TSOP (20x12mm)
- 48 Ball FBGA (6x8mm, 0.8mm Ball Pitch)
- 64 Ball FBGA (13x11mm, 1.0mm Ball Pitch)
GENERAL DESCRIPTION
The K8P6415UQB featuring single 3.0V power supply, is an
64Mbit NOR-type Flash Memory organized as 4M x16. The
memory architecture of the device is designed to divide its
memory arrays into 142 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8P6415UQB NOR Flash consists
of four banks. This device is capable of reading data from one
bank while programming or erasing in the other banks.
The K8P6415UQB offers fast page access time of 20~30ns with
random access time of 60~70ns. The device′s fast access
times allow high speed microprocessors to operate without wait
states. The device performs a program operation in unit of 16
bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed
within typically 0.7 sec. The device requires 17mA as program/
erase current in the commercial and industrial temperature
ranges.
The K8P6415UQB NOR Flash Memory is created by using
Samsung's advanced CMOS process technology. This device is
available in 48 Pin TSOP package and 48/64 Ball FBGA pack-
age. The device is compatible with EPROM applications to
require high-density and cost-effective non-volatile read/write
storage solutions.
PIN DESCRIPTION
Pin Name
A0 - A21
DQ0 - DQ15
CE
OE
RESET
RY/BY
WE
WP/ACC
Vcc
V
SS
N.C
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Hardware Write Protection/Program Acceleration
Power Supply
Ground
No Connection
Pin Function
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
3
Revision 1.4
June 2007
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