UPD48288218FF-EF25-DW1-A datasheet, PDF

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UPD48288218FF-EF25-DW1-A: DescriptionDDR DRAM; Categorystorage storage; File Size856KB，50 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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UPD48288218FF-EF25-DW1-A Overview

DDR DRAM

UPD48288218FF-EF25-DW1-A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
package instruction	BGA, BGA144,12X18,40/32
Reach Compliance Code	unknown
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B144
memory density	301989888 bit
Memory IC Type	DDR DRAM
memory width	18
Number of terminals	144
word count	16777216 words
character code	16000000
organize	16MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA144,12X18,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY
power supply	1.5,1.8,2.5 V
Certification status	Not Qualified
Continuous burst length	2,4,8
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

UPD48288218FF-EF25-DW1-A Preview

Datasheet

PD48288209-A

PD48288218-A

PD48288236-A

288M-BIT Low Latency DRAM

Common I/O

Description

The

PD48288209-A is a 33,554,432-word by 9 bit, the

PD48288218-A is a 16,777,216 word by 18 bit and the

R10DS0156EJ0100

Rev.1.00

Feb 01, 2013

PD48288236-A is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced

CMOS technology using one-transistor memory cell.

The

PD48288209-A,

PD48288218-A and

PD48288236-A integrate unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and

CK#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

Specification

•

Density: 288M bit

•

Organization

Common I/O: 4M words x 9 bits x 8 banks

2M words x 18 bits x 8 banks

1M words x 36 bits x 8 banks

•

Operating frequency: 400 / 300 MHz

•

Interface: HSTL I/O

•

Package: 144-pin TAPE FBGA

Package size: 18.5 x 11

Leaded and Lead free

2.5 V V

EXT

1.8 V V

1.5 V or 1.8 V V

Auto Refresh

8192 cycle / 32 ms for each bank

64K cycle / 32 ms for total

Features

•

SRAM-type interface

•

Double-data-rate architecture

•

PLL circuitry

•

Cycle time: 2.5 ns @ t

= 20 ns

3.3 ns @ t

= 20 ns

•

Non-multiplexed addresses

•

Multiplexing option is available.

•

Data mask for WRITE commands

•

Differential input clocks (CK and CK#)

•

Differential input data clocks (DK and DK#)

•

Data valid signal (QVLD)

•

Programmable burst length: 2 / 4 / 8 (x9 / x18)

2 / 4 (x36)

•

User programmable impedance output (25

- 60

Ω)

•

JTAG boundary scan

•

Power supply

•

Refresh command

•

Operating case temperature : Tc = 0 to 95°C

R10DS0156EJ0100 Rev.1.00

Feb 01, 2013

Page 1 of 49

PD48288209-A,

PD48288218-A,

PD48288236-A

Ordering Information

Part number

Cycle

Clock

Random Organization Core Supply Core Supply Output Supply

Cycle

(word x bit)

Voltage

EXT

)

MHz

300

400

300

400

300

400

300

8 M x 36

16 M x 18

32 M x 9

16 M x 18

8 M x 36

32 M x 9

1.5 ± 0.1

2.5 + 0.13

2.5 – 0.12

Voltage

)

1.8 ± 0.1

Voltage

1.8 ± 0.1

144-pin

TAPE FBGA

(18.5 x 11)

Lead-free

Package

Time Frequency

PD48288209FF-E33-DW1-A

PD48288218FF-E33-DW1-A

PD48288236FF-E33-DW1-A

PD48288209FF-EF25-DW1-A

PD48288209FF-EF33-DW1-A

PD48288218FF-EF25-DW1-A

PD48288218FF-EF33-DW1-A

PD48288236FF-EF25-DW1-A

PD48288236FF-EF33-DW1-A

3.3

2.5

3.3

2.5

3.3

2.5

3.3

Remark

Products with –A at the end of part number are lead-free products.

R10DS0156EJ0100 Rev.1.00

Feb 01, 2013

Page 2 of 49

PD48288209-A,

PD48288218-A,

PD48288236-A

Pin Configurations

# indicates active LOW signal.

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x36]

REF

(A22)

(A21)

BA2

DK0

DK1

REF#

WE#

A18

A15

REF

Note

DQ8

DQ10

DQ12

DQ14

DQ16

DK0#

DK1#

CS#

A16

DQ24

DQ22

QK1

DQ20

DQ18

EXT

DQ9

DQ11

DQ13

DQ15

DQ17

A17

DQ25

DQ23

QK1#

DQ21

DQ19

EXT

DQ1

DQ3

QK0#

DQ5

DQ7

A12

DQ35

DQ33

DQ31

DQ29

DQ27

EXT

TMS

DQ0

DQ2

QK0

DQ4

DQ6

BA0

BA1

A14

A11

DQ34

DQ32

DQ30

DQ28

DQ26

TDO

TCK

(A20)

CK#

A13

A10

(A19)

TDI

Note

QVLD

Note

Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input

signal. This may optionally be connected to V

, or left open.

CK, CK#

CS#

WE#

REF#

A0–A18

A19–A22

BA0–BA2

DQ0–DQ35

DK0–DK1, DK0#–DK1#

QK0–QK1, QK0#–QK1#

QVLD

: Input clock

: Chip select

: WRITE command

: Refresh command

: Address inputs

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

: Output impedance matching

TMS

TDI

TCK

TDO

REF

EXT

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: DQ Power Supply

: Ground

: DQ Ground

: Power Supply

R10DS0156EJ0100 Rev.1.00

Feb 01, 2013

Page 3 of 49

PD48288209-A,

PD48288218-A,

PD48288236-A

# indicates active LOW signal.

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x18]

REF

(A22)

(A21)

BA2

Note 2

Note 1

DNU

Note 2

Note 3

EXT

DQ4

DQ5

DQ6

DQ7

DQ8

A17

DQ14

DQ15

QK1#

DQ16

DQ17

EXT

DQ0

DQ1

QK0#

DQ2

DQ3

A12

DQ9

DQ10

DQ11

DQ12

DQ13

EXT

TMS

DNU

QK0

DNU

BA0

BA1

A14

A11

DNU

TDO

Note 3

TCK

(A20)

CK#

A13

A10

A19

TDI

Note 1

QVLD

REF#

WE#

A18

A15

REF

DK#

CS#

A16

DNU

QK1

DNU

Note 3

Notes 1.

Reserved for future use. This signal is internally connected and has parasitic characteristics of an address

input signal. This may optionally be connected to V

, or left open.

No function. This signal is internally connected and has parasitic characteristics of a clock input signal.

This may optionally be connected to V

, or left open.

Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may

optionally be connected to V

, or left open.

CK, CK#

CS#

WE#

REF#

A0–A19

A20–A22

BA0–BA2

DQ0–DQ17

DK, DK#

QK0–QK1, QK0#–QK1#

QVLD

: Input clock

: Chip select

: WRITE command

: Refresh command

: Address inputs

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

: Output impedance matching

TMS

TDI

TCK

TDO

REF

EXT

DNU

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: DQ Power Supply

: Ground

: DQ Ground

: Power Supply

: No function

: Do not use

R10DS0156EJ0100 Rev.1.00

Feb 01, 2013

Page 4 of 49

PD48288209-A,

PD48288218-A,

PD48288236-A

# indicates active LOW signal.

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x9]

REF

(A22)

(A21)

BA2

Note 2

Note 1

Note1

DNU

Note 2

Note 3

EXT

DNU

A17

DNU

EXT

Note 3

EXT

DQ0

DQ1

QK0#

DQ2

DQ3

A12

DQ4

DQ5

DQ6

DQ7

DQ8

EXT

TMS

DNU

QK0

DNU

BA0

BA1

A14

A11

DNU

TDO

Note 3

TCK

A20

QVLD

CK#

A13

A10

A19

TDI

Note 3

REF#

WE#

A18

A15

REF

DK#

CS#

A16

DNU

Note 3

Notes 1.

Reserved for future use. This signal is internally connected and has parasitic characteristics of an address

input signal. This may optionally be connected to V

, or left open.

No function. This signal is internally connected and has parasitic characteristics of a clock input signal.

This may optionally be connected to V

, or left open.

Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may

optionally be connected to V

, or left open.

CK, CK#

CS#

WE#

REF#

A0–A20

A21–A22

BA0–BA2

DQ0–DQ8

DK, DK#

QK0, QK0#

QVLD

: Input clock

: Chip select

: WRITE command

: Refresh command

: Address inputs

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

: Output impedance matching

TMS

TDI

TCK

TDO

REF

EXT

DNU

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: DQ Power Supply

: Ground

: DQ Ground

: Power Supply

: No function

: Do not use

R10DS0156EJ0100 Rev.1.00

Feb 01, 2013

Page 5 of 49

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

UPD48288218FF-EF25-DW1-A Related Products

	UPD48288218FF-EF25-DW1-A	UPD48288218FF-E33-DW1-A	UPD48288218FF-EF33-DW1-A	UPD48288236FF-E33-DW1-A	UPD48288209FF-EF25-DW1-A	UPD48288209FF-E33-DW1-A	UPD48288236FF-EF25-DW1-A	UPD48288236FF-EF33-DW1-A	UPD48288209FF-EF33-DW1-A
Description	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
package instruction	BGA, BGA144,12X18,40/32	TBGA, BGA144,12X18,40/32	BGA, BGA144,12X18,40/32	TBGA, BGA144,12X18,40/32	BGA, BGA144,12X18,40/32	TBGA, BGA144,12X18,40/32	BGA, BGA144,12X18,40/32	BGA, BGA144,12X18,40/32	BGA, BGA144,12X18,40/32
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum clock frequency (fCLK)	400 MHz	300 MHz	300 MHz	300 MHz	400 MHz	300 MHz	400 MHz	300 MHz	300 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144
memory density	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	18	18	18	36	9	9	36	36	9
Number of terminals	144	144	144	144	144	144	144	144	144
word count	16777216 words	16777216 words	16777216 words	8388608 words	33554432 words	33554432 words	8388608 words	8388608 words	33554432 words
character code	16000000	16000000	16000000	8000000	32000000	32000000	8000000	8000000	32000000
organize	16MX18	16MX18	16MX18	8MX36	32MX9	32MX9	8MX36	8MX36	32MX9
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	TBGA	BGA	TBGA	BGA	TBGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY, THIN PROFILE	GRID ARRAY	GRID ARRAY, THIN PROFILE	GRID ARRAY	GRID ARRAY, THIN PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.5,1.8,2.5 V	1.8,2.5 V	1.5,1.8,2.5 V	1.8,2.5 V	1.5,1.8,2.5 V	1.8,2.5 V	1.5,1.8,2.5 V	1.5,1.8,2.5 V	1.5,1.8,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	1 mm	0.8 mm	1 mm	0.8 mm	1 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Continuous burst length	2,4,8	2,4,8	2,4,8	2,4	-	-	2,4	2,4	-
Objectid	-	-	-	-	1277592847	1277592846	1277592853	1277592854	1277592848
ECCN code	-	-	-	-	EAR99	EAR99	EAR99	EAR99	EAR99

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