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UPD48288218FF-E33-DW1-A

Description
DDR DRAM
Categorystorage    storage   
File Size856KB,50 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
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UPD48288218FF-E33-DW1-A Overview

DDR DRAM

UPD48288218FF-E33-DW1-A Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerRenesas Electronics Corporation
package instructionTBGA, BGA144,12X18,40/32
Reach Compliance Codeunknown
access modeMULTI BANK PAGE BURST
Other featuresAUTO REFRESH; IT ALSO REQUIRES AT 2.5V
Maximum clock frequency (fCLK)300 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B144
length18.5 mm
memory density301989888 bit
Memory IC TypeDDR DRAM
memory width18
Number of functions1
Number of ports1
Number of terminals144
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
organize16MX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA144,12X18,40/32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
power supply1.8,2.5 V
Certification statusNot Qualified
Maximum seat height1.17 mm
Continuous burst length2,4,8
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width11 mm

UPD48288218FF-E33-DW1-A Preview

Datasheet
μ
PD48288209-A
μ
PD48288218-A
μ
PD48288236-A
288M-BIT Low Latency DRAM
Common I/O
Description
The
μ
PD48288209-A is a 33,554,432-word by 9 bit, the
μ
PD48288218-A is a 16,777,216 word by 18 bit and the
R10DS0156EJ0100
Rev.1.00
Feb 01, 2013
μ
PD48288236-A is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced
CMOS technology using one-transistor memory cell.
The
μ
PD48288209-A,
μ
PD48288218-A and
μ
PD48288236-A integrate unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and
CK#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
Specification
Density: 288M bit
Organization
-
Common I/O: 4M words x 9 bits x 8 banks
2M words x 18 bits x 8 banks
1M words x 36 bits x 8 banks
Operating frequency: 400 / 300 MHz
Interface: HSTL I/O
Package: 144-pin TAPE FBGA
-
-
-
-
-
-
-
-
Package size: 18.5 x 11
Leaded and Lead free
2.5 V V
EXT
1.8 V V
DD
1.5 V or 1.8 V V
DD
Q
Auto Refresh
8192 cycle / 32 ms for each bank
64K cycle / 32 ms for total
Features
SRAM-type interface
Double-data-rate architecture
PLL circuitry
Cycle time: 2.5 ns @ t
RC
= 20 ns
3.3 ns @ t
RC
= 20 ns
Non-multiplexed addresses
Multiplexing option is available.
Data mask for WRITE commands
Differential input clocks (CK and CK#)
Differential input data clocks (DK and DK#)
Data valid signal (QVLD)
Programmable burst length: 2 / 4 / 8 (x9 / x18)
2 / 4 (x36)
User programmable impedance output (25
Ω
- 60
Ω)
JTAG boundary scan
Power supply
Refresh command
Operating case temperature : Tc = 0 to 95°C
R10DS0156EJ0100 Rev.1.00
Feb 01, 2013
Page 1 of 49
μ
PD48288209-A,
μ
PD48288218-A,
μ
PD48288236-A
Ordering Information
Part number
Cycle
Clock
Random Organization Core Supply Core Supply Output Supply
Cycle
(word x bit)
Voltage
(V
EXT
)
ns
MHz
300
300
300
400
300
400
300
400
300
ns
20
20
20
20
20
20
20
20
20
8 M x 36
16 M x 18
32 M x 9
16 M x 18
8 M x 36
32 M x 9
1.5 ± 0.1
V
2.5 + 0.13
2.5 – 0.12
Voltage
(V
DD
)
V
1.8 ± 0.1
Voltage
(V
DD
Q)
V
1.8 ± 0.1
144-pin
TAPE FBGA
(18.5 x 11)
Lead-free
Package
Time Frequency
μ
PD48288209FF-E33-DW1-A
μ
PD48288218FF-E33-DW1-A
μ
PD48288236FF-E33-DW1-A
μ
PD48288209FF-EF25-DW1-A
μ
PD48288209FF-EF33-DW1-A
μ
PD48288218FF-EF25-DW1-A
μ
PD48288218FF-EF33-DW1-A
μ
PD48288236FF-EF25-DW1-A
μ
PD48288236FF-EF33-DW1-A
3.3
3.3
3.3
2.5
3.3
2.5
3.3
2.5
3.3
Remark
Products with –A at the end of part number are lead-free products.
R10DS0156EJ0100 Rev.1.00
Feb 01, 2013
Page 2 of 49
μ
PD48288209-A,
μ
PD48288218-A,
μ
PD48288236-A
Pin Configurations
# indicates active LOW signal.
144-pin TAPE FBGA (18.5 x 11)
(Top View) [Common I/O x36]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
(A22)
(A21)
A5
A8
BA2
DK0
DK1
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
Note
Note
2
V
SS
DQ8
DQ10
DQ12
DQ14
DQ16
A6
A9
DK0#
DK1#
CS#
A16
DQ24
DQ22
QK1
DQ20
DQ18
ZQ
3
V
EXT
DQ9
DQ11
DQ13
DQ15
DQ17
A7
V
SS
V
DD
V
DD
V
SS
A17
DQ25
DQ23
QK1#
DQ21
DQ19
V
EXT
4
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
5
6
7
8
9
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
10
V
EXT
DQ1
DQ3
QK0#
DQ5
DQ7
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ35
DQ33
DQ31
DQ29
DQ27
V
EXT
11
TMS
DQ0
DQ2
QK0
DQ4
DQ6
A1
A4
BA0
BA1
A14
A11
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
12
TCK
V
DD
V
TT
V
SS
(A20)
A0
A3
CK
CK#
A13
A10
(A19)
DM
V
SS
V
TT
V
DD
TDI
Note
Note
QVLD
Note
Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input
signal. This may optionally be connected to V
SS
, or left open.
CK, CK#
CS#
WE#
REF#
A0–A18
A19–A22
BA0–BA2
DQ0–DQ35
DK0–DK1, DK0#–DK1#
DM
QK0–QK1, QK0#–QK1#
QVLD
ZQ
: Input clock
: Chip select
: WRITE command
: Refresh command
: Address inputs
: Reserved for the future
: Bank address input
: Data input/output
: Input data clock
: Input data Mask
: Output data clock
: Data Valid
: Output impedance matching
TMS
TDI
TCK
TDO
V
REF
V
EXT
V
DD
V
DD
Q
V
SS
V
SS
Q
V
TT
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: DQ Power Supply
: Ground
: DQ Ground
: Power Supply
R10DS0156EJ0100 Rev.1.00
Feb 01, 2013
Page 3 of 49
μ
PD48288209-A,
μ
PD48288218-A,
μ
PD48288236-A
# indicates active LOW signal.
144-pin TAPE FBGA (18.5 x 11)
(Top View) [Common I/O x18]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
(A22)
(A21)
A5
A8
BA2
NF
Note 2
Note 1
Note 1
2
V
SS
DNU
DNU
DNU
DNU
DNU
A6
A9
NF
Note 2
Note 3
Note 3
Note 3
Note 3
Note 3
3
V
EXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
V
SS
V
DD
V
DD
V
SS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
V
EXT
4
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
5
6
7
8
9
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
10
V
EXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
V
EXT
11
TMS
DNU
DNU
QK0
DNU
DNU
A1
A4
BA0
BA1
A14
A11
DNU
DNU
DNU
DNU
DNU
TDO
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
12
TCK
V
DD
V
TT
V
SS
(A20)
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Note 1
QVLD
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
DNU
DNU
QK1
DNU
DNU
ZQ
Note 3
Note 3
Note 3
Note 3
Notes 1.
Reserved for future use. This signal is internally connected and has parasitic characteristics of an address
input signal. This may optionally be connected to V
SS
, or left open.
2.
No function. This signal is internally connected and has parasitic characteristics of a clock input signal.
This may optionally be connected to V
SS
, or left open.
3.
Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may
optionally be connected to V
SS
, or left open.
CK, CK#
CS#
WE#
REF#
A0–A19
A20–A22
BA0–BA2
DQ0–DQ17
DK, DK#
DM
QK0–QK1, QK0#–QK1#
QVLD
ZQ
: Input clock
: Chip select
: WRITE command
: Refresh command
: Address inputs
: Reserved for the future
: Bank address input
: Data input/output
: Input data clock
: Input data Mask
: Output data clock
: Data Valid
: Output impedance matching
TMS
TDI
TCK
TDO
V
REF
V
EXT
V
DD
V
DD
Q
V
SS
V
SS
Q
V
TT
NF
DNU
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: DQ Power Supply
: Ground
: DQ Ground
: Power Supply
: No function
: Do not use
R10DS0156EJ0100 Rev.1.00
Feb 01, 2013
Page 4 of 49
μ
PD48288209-A,
μ
PD48288218-A,
μ
PD48288236-A
# indicates active LOW signal.
144-pin TAPE FBGA (18.5 x 11)
(Top View) [Common I/O x9]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
(A22)
(A21)
A5
A8
BA2
NF
Note 2
Note 1
Note1
2
V
SS
DNU
DNU
DNU
DNU
DNU
A6
A9
NF
Note 2
Note 3
Note 3
3
V
EXT
DNU
DNU
DNU
DNU
DNU
A7
V
SS
V
DD
V
DD
V
SS
A17
DNU
DNU
DNU
DNU
DNU
V
EXT
Note 3
Note 3
Note 3
Note 3
4
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
5
6
7
8
9
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
10
V
EXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
V
EXT
11
TMS
DNU
DNU
QK0
DNU
DNU
A1
A4
BA0
BA1
A14
A11
DNU
DNU
DNU
DNU
DNU
TDO
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
DNU
DNU
DNU
DNU
DNU
ZQ
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Notes 1.
2.
3.
Reserved for future use. This signal is internally connected and has parasitic characteristics of an address
input signal. This may optionally be connected to V
SS
, or left open.
No function. This signal is internally connected and has parasitic characteristics of a clock input signal.
This may optionally be connected to V
SS
, or left open.
Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may
optionally be connected to V
SS
, or left open.
CK, CK#
CS#
WE#
REF#
A0–A20
A21–A22
BA0–BA2
DQ0–DQ8
DK, DK#
DM
QK0, QK0#
QVLD
ZQ
: Input clock
: Chip select
: WRITE command
: Refresh command
: Address inputs
: Reserved for the future
: Bank address input
: Data input/output
: Input data clock
: Input data Mask
: Output data clock
: Data Valid
: Output impedance matching
TMS
TDI
TCK
TDO
V
REF
V
EXT
V
DD
V
DD
Q
V
SS
V
SS
Q
V
TT
NF
DNU
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: DQ Power Supply
: Ground
: DQ Ground
: Power Supply
: No function
: Do not use
R10DS0156EJ0100 Rev.1.00
Feb 01, 2013
Page 5 of 49

UPD48288218FF-E33-DW1-A Related Products

UPD48288218FF-E33-DW1-A UPD48288218FF-EF25-DW1-A UPD48288218FF-EF33-DW1-A UPD48288236FF-E33-DW1-A UPD48288209FF-EF25-DW1-A UPD48288209FF-E33-DW1-A UPD48288236FF-EF25-DW1-A UPD48288236FF-EF33-DW1-A UPD48288209FF-EF33-DW1-A
Description DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to conform to
package instruction TBGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32 TBGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32 TBGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32 BGA, BGA144,12X18,40/32
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknown
Maximum clock frequency (fCLK) 300 MHz 400 MHz 300 MHz 300 MHz 400 MHz 300 MHz 400 MHz 300 MHz 300 MHz
I/O type COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 code R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144 R-PBGA-B144
memory density 301989888 bit 301989888 bit 301989888 bit 301989888 bit 301989888 bit 301989888 bit 301989888 bit 301989888 bit 301989888 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width 18 18 18 36 9 9 36 36 9
Number of terminals 144 144 144 144 144 144 144 144 144
word count 16777216 words 16777216 words 16777216 words 8388608 words 33554432 words 33554432 words 8388608 words 8388608 words 33554432 words
character code 16000000 16000000 16000000 8000000 32000000 32000000 8000000 8000000 32000000
organize 16MX18 16MX18 16MX18 8MX36 32MX9 32MX9 8MX36 8MX36 32MX9
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TBGA BGA BGA TBGA BGA TBGA BGA BGA BGA
Encapsulate equivalent code BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32 BGA144,12X18,40/32
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE GRID ARRAY GRID ARRAY GRID ARRAY, THIN PROFILE GRID ARRAY GRID ARRAY, THIN PROFILE GRID ARRAY GRID ARRAY GRID ARRAY
power supply 1.8,2.5 V 1.5,1.8,2.5 V 1.5,1.8,2.5 V 1.8,2.5 V 1.5,1.8,2.5 V 1.8,2.5 V 1.5,1.8,2.5 V 1.5,1.8,2.5 V 1.5,1.8,2.5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
surface mount YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Terminal form BALL BALL BALL BALL BALL BALL BALL BALL BALL
Terminal pitch 1 mm 0.8 mm 0.8 mm 1 mm 0.8 mm 1 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Continuous burst length 2,4,8 2,4,8 2,4,8 2,4 - - 2,4 2,4 -
Objectid - - - - 1277592847 1277592846 1277592853 1277592854 1277592848
ECCN code - - - - EAR99 EAR99 EAR99 EAR99 EAR99
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