|
LP3984ITPX-1.8 |
LP3984ITP-2.9 |
| Description |
IC VREG 1.8 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PBGA4, 0.500 MM HEIGHT, MICRO, BUMP, SMD-4, Fixed Positive Single Output LDO Regulator |
IC VREG 2.9 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PBGA4, 0.500 MM HEIGHT, MICRO, BUMP, SMD-4, Fixed Positive Single Output LDO Regulator |
| Is it Rohs certified? |
conform to |
incompatible |
| Maker |
National Semiconductor(TI ) |
National Semiconductor(TI ) |
| package instruction |
VFBGA, BGA4,2X2,20 |
0.500 MM HEIGHT, MICRO, BUMP, SMD-4 |
| Reach Compliance Code |
compliant |
_compli |
| ECCN code |
EAR99 |
EAR99 |
| Adjustability |
FIXED |
FIXED |
| Maximum drop-back voltage 1 |
0.12 V |
0.12 V |
| Maximum absolute input voltage |
6.5 V |
6.5 V |
| Maximum input voltage |
6 V |
6 V |
| Minimum input voltage |
2.5 V |
2.5 V |
| JESD-30 code |
R-PBGA-B4 |
R-PBGA-B4 |
| JESD-609 code |
e1 |
e0 |
| length |
0.98 mm |
0.98 mm |
| Maximum grid adjustment rate |
0.0054% |
0.0048% |
| Maximum load regulation |
0.0054% |
0.0087% |
| Humidity sensitivity level |
1 |
1 |
| Number of functions |
1 |
1 |
| Output times |
1 |
1 |
| Number of terminals |
4 |
4 |
| Working temperatureTJ-Max |
125 °C |
125 °C |
| Maximum output current 1 |
0.15 A |
0.15 A |
| Maximum output voltage 1 |
1.836 V |
2.958 V |
| Minimum output voltage 1 |
1.764 V |
2.842 V |
| Nominal output voltage 1 |
1.8 V |
2.9 V |
| Package body material |
PLASTIC/EPOXY |
PLASTIC/EPOXY |
| encapsulated code |
VFBGA |
VFBGA |
| Encapsulate equivalent code |
BGA4,2X2,20 |
BGA4,2X2,20 |
| Package shape |
RECTANGULAR |
RECTANGULAR |
| Package form |
GRID ARRAY, VERY THIN PROFILE, FINE PITCH |
GRID ARRAY, VERY THIN PROFILE, FINE PITCH |
| method of packing |
TAPE AND REEL |
TAPE AND REEL |
| Peak Reflow Temperature (Celsius) |
260 |
260 |
| Certification status |
Not Qualified |
Not Qualified |
| Regulator type |
FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR |
FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR |
| Maximum seat height |
0.575 mm |
0.575 mm |
| surface mount |
YES |
YES |
| technology |
CMOS |
CMOS |
| Terminal surface |
Tin/Silver/Copper (Sn/Ag/Cu) |
Tin/Lead (Sn63Pb37) |
| Terminal form |
BALL |
BALL |
| Terminal pitch |
0.5 mm |
0.5 mm |
| Terminal location |
BOTTOM |
BOTTOM |
| Maximum time at peak reflow temperature |
40 |
40 |
| Maximum voltage tolerance |
2% |
2% |
| width |
0.879 mm |
0.879 mm |