FT61024-100LM datasheet, PDF - EEWORLD Datasheet

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FT61024-100LM: DescriptionStandard SRAM, 128KX8, 100ns, CMOS, PQCC32, 0.450 X 0.550 INCH, LCC-32; Categorystorage storage; File Size311KB，15 Pages; ManufacturerForce Technologies Ltd.

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FT61024-100LM Overview

Standard SRAM, 128KX8, 100ns, CMOS, PQCC32, 0.450 X 0.550 INCH, LCC-32

FT61024-100LM Parametric

Parameter Name	Attribute value
Maker	Force Technologies Ltd.
Parts packaging code	QFJ
package instruction	QCCN,
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	100 ns
JESD-30 code	R-PQCC-N32
length	13.97 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.905 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.43 mm

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FT61024

HIGH SPEED 128K x 8

DUAL CHIP ENABLE

CMOS STATIC RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 15/20/25/35 ns (Commercial)

— 20/25/35/45 ns (Industrial)

— 20/25/35/45/55/70/85/100/120 ns (Military)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down

Packages

—32-Pin 300 mil DIP and SOJ

—32-Pin 400 mil SOJ

—32-Pin 600 mil Ceramic DIP

—32-Pin 400 mil Ceramic DIP

—32-Pin Solder Seal Flatpack

—32-Pin LCC (450 x 550 mil)

—32-Pin Ceramic SOJ

DESCRIPTION

The FT61024 is a 1,048,576-bit high-speed CMOS

static RAM organised as 128Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 15 nanoseconds permit greatly en-

hanced system operating speeds. CMOS is utilised to

reduce power consumption to a low level.The FT61024

is a member of a family ofForce Ram products offer-

ing fast access times.

The FT61024 device provides asynchronous opera-

tions with matching access and cycle times. Memory

locations are specified on address pins A

to A

Reading is accomplished by device selection

low

(

and CE

high) and output enabling (

OE)

while write

enable (WE) remains HIGH. By presenting the ad-

dress under these conditions, the dat a in the ad-

dressed memory location is presented on the dat a

input/output pins. The input/output pins st ay in the

HIGH Z state when either

is HIGH or

or CE

is LOW.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (P300, C10, C11),

SOJ (J300, J400, CJ1),

SOLDER SEAL

FLATPACK (FS-3) SIMILAR

LCC (L6)

REV 1

1/15

2008

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