Integrated
Circuit
Systems, Inc.
ICS932S421B
PCIe Gen 2 main Clock for Intel-based Servers
Recommended Application:
PCIe Gen 2 & FBD compliant CK410B (CK410B+) clock for
Intel-based servers
Output Features:
•
4 - 0.7V current-mode differential CPU pairs
•
5 - 0.7V current-mode differential SRC pair
•
4 - PCI (33MHz)
•
3 - PCICLK_F, (33MHz) free-running
•
1 - 48MHz
•
2 - REF, 14.318MHz
Features/Benefits:
•
Supports spread spectrum modulation, 0 to -0.5% down
spread
•
•
•
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Pin Configuration
FS_A
0
1
0
1
0
1
0
1
2
Key Specifications:
•
PCIe Gen 2 compliant SRC outputs
•
FBD 2 compliant CPU clocks
•
CPU cycle-cycle jitter: < 50ps
•
SRC cycle-cycle jitter: < 125ps
•
PCI cycle-cycle jitter: < 500ps
•
CPU output skew: < 50ps
•
SRC output skew: < 250ps
•
± 300ppm frequency accuracy on all outputs except
48MHz
•
± 100ppm frequency accuracy on 48MHz
Functionality
FS_C
0
0
0
0
1
1
1
1
1
FS_B
0
0
1
1
0
0
1
1
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
SRC
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
REF
MHz
MHz
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
Reserved
U
SB
MHz
48.000
48.000
48.000
48.000
48.000
48.000
48.000
1. FS_B and FS_C are three-level inputs. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_A is a low-threshold input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
48MHz
GND48
VDDSRC
SRCCLKT0
SRCCLKC0
SRCCLKC1
SRCCLKT1
GNDSRC
SRCCLKT2
SRCCLKC2
SRCCLKC3
SRCCLKT3
VDDSRC
SRCCLKT4
SRCCLKC4
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_C/TEST_SEL
REF0
REF1
VDDREF
X1
X2
GNDREF
FS_B/TEST_MODE
FS_A
VDDCPU
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GNDCPU
CPUCLKT2
CPUCLKC2
VDDCPU
CPUCLKT3
CPUCLKC3
VDDA
GNDA
IREF
NC
Vtt_PwrGd#/PD
SDATA
SCLK
1340B—06/13/07
56-pin SSOP & TSSOP
ICS932S421
Integrated
Circuit
Systems, Inc.
ICS932S421B
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
48MHz
GND48
VDDSRC
SRCCLKT0
SRCCLKC0
SRCCLKC1
SRCCLKT1
GNDSRC
SRCCLKT2
SRCCLKC2
SRCCLKC3
SRCCLKT3
VDDSRC
SRCCLKT4
SRCCLKC4
VDDSRC
PIN TYPE
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power pin for the 48MHz output.3.3V
48MHz clock output.
Ground pin for the 48MHz outputs
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Complement clock of differential push-pull SRC clock pair.
True clock of differential SRC clock pair.
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
1340B—06/13/07
2
Integrated
Circuit
Systems, Inc.
ICS932S421B
Pin Description (Continued)
Pin #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PIN NAME
SCLK
SDATA
Vtt_PwrGd#/PD
NC
IREF
GNDA
VDDA
CPUCLKC3
CPUCLKT3
VDDCPU
CPUCLKC2
CPUCLKT2
GNDCPU
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
VDDCPU
FS_A
Type
IN
I/O
IN
N/A
OUT
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
Pin Description
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
No Connection.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real
time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
14.318 MHz reference clock.
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
49
50
51
52
53
54
55
FS_B/TEST_MODE
GNDREF
X2
X1
VDDREF
REF1
REF0
IN
PWR
OUT
IN
PWR
OUT
OUT
56
FS_C/TEST_SEL
IN
1340B—06/13/07
3
Integrated
Circuit
Systems, Inc.
ICS932S421B
General Description
ICS932S421B
is a main clock synthesizer for CK410B-generation Intel server platforms.
ICS932S421B
is driven with a
14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100. The 48 MHz USB clock is an exact
48.000 MHz clock. The
ICS932S421B
generates all other clocks with less the +/- 300 ppm error.
Block Diagram
REF(1:0)
X1
X2
XTAL
OSC.
48MHz
FIXED PLL
DIVIDER
CPU PLL
DIVIDERS
CPUCLK(3:0)
SRC/PCI
PLL
SRCCLK(4:0)
DIVIDERS
PCICLK(3:0), PCICLK_F(2:0)
FS(C:A)
TEST_SEL
CONTROL
LOGIC
VTT_PWRGD#/PD
SDATA
SCLK
IREF
Power Groups
Pin Number
VDD
GND
53
50
1,8
2,7
15,25,28
20
35
34
12
14
47,44,38
41
1340B—06/13/07
Description
Xtal, Ref
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL_48
CPUCLK clocks
4
Integrated
Circuit
Systems, Inc.
ICS932S421B
Absolute Max
Symbol
VDD_A
Parameter
3.3V Core Supply Voltage
Min
GND - 0.5
-65
0
2000
Max
V
DD
+ 0.5V
V
DD
+ 0.5V
150
70
115
Units
V
V
C
°C
°C
V
°
VDD_In 3.3V Logic Input Supply Voltage
Ts
Storage Temperature
Tambient
Ambient Operating Temp
Tcase
Case Temperature
Input ESD protection
ESD prot
human body model
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Low Threshold Input High
Voltage
Low Threshold Input Low
Voltage
Operating Supply Current
Powerdown Current
Input Frequency
3
Pin Inductance
1
Input Capacitance
1
CONDITIONS
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-
up resistors
V
IN
= 0 V; Inputs with pull-up
resistors
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%, Full Load
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Max. Voltage on SCLK/SDAT
@ I
PULLUP
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
MIN
2
V
SS
- 0.3
-5
-5
-200
0.7
V
SS
- 0.3
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS NOTES
V
V
uA
uA
uA
V
IH_FS
V
IL_FS
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
T
STAB
V
DD
+ 0.3
0.35
350
90
15
7
5
5
5
1.8
V
V
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
us
ns
ns
V
V
mA
ns
ns
3
1
1
1
1
1,2
1
1
1
2
1
1
1
1
1
Clk Stabilization
1,2
Modulation Frequency
Tdrive_PD#
30
33
300
5
5
5.5
0.4
Tfall_Pd#
Trise_Pd#
SMBus Voltage
V
IMAX
Low-level Output Voltage
V
OLSMBUS
Current sinking at V
OL
= 0.4 V I
PULLUP
SCLK/SDATA
T
RI2C
Clock/Data Rise Time
SCLK/SDATA
T
FI2C
Clock/Data Fall Time
1
2
3
4
1000
300
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs.
1340B—06/13/07
5
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