MT57W512H36BF-5 datasheet, PDF

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MT57W512H36BF-5: DescriptionDDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size495KB，24 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT57W512H36BF-5 Overview

DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

MT57W512H36BF-5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	BGA
package instruction	13 X 15 MM, 1 MM PITCH, FBGA-165
Contacts	165
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Minimum standby current	1.7 V
Maximum slew rate	0.445 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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ADVANCE

‡

2 MEG x 8, 1 MEG x 18, 512K x 36

1.8V V

, HSTL, DDRIIb2 SRAM

18Mb

DDRII CIO SRAM

2-Word Burst

FEATURES

• 18Mb Density (2 Meg x 8, 1 Meg x 18, 512K x 36)

• DLL circuitry for wide-output, data valid window

and future frequency scaling

• Pipelined, double-data rate operation

• Common data input/output bus

• Fast clock to valid data times

• Full data coherency, providing most current data

• Two-tick burst for low DDR transaction size

• Permits up to one new data request per clock cycle

• Two input clocks (K and K#) for precise DDR timing

at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• +1.8V core and HSTL I/O

• Clock-stop capability with

restart

• 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package

• User programmable impedance output

• JTAG boundary scan

MT57W2MH8B

MT57W1MH18B

MT57W512H36B

165-BALL FBGA

GENERAL DESCRIPTION

The Micron® DDRII (Double Data Rate) synchro-

nous, pipelined, burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS pro-

cess. The DDR SRAM integrates an SRAM core with ad-

vanced synchronous peripheral circuitry and a burst

counter. All synchronous inputs pass through registers

controlled by an input clock pair (K and K#) and are

latched on the rising edge of K and K#. The synchronous

inputs include all addresses, all data inputs, active LOW

load (LD#), read/write (R/W#), and active LOW byte writes

or nybble writes (BWx# or NWx#). Write data is registered

on the rising edges of both K and K#. Read data is driven

on the rising edge of C and C# if provided, or on the rising

edge of K and K#, if C and C# are not provided.

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical

pins as the data inputs D) are tightly matched to the

output data clocks C and C#, eliminating the need for

separately capturing data from each individual DDR

SRAM in the system design.

Additional write registers are incorporated to enhance

pipelined WRITE cycles and reduce READ-to-WRITE turn-

around time. WRITE cycles are self-timed.

OPTIONS

• Clock Cycle Timing

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200MHz)

6ns (167 MHz)

7.5ns (133 MHz)

• Configurations

2 Meg x 8

1 Meg x 18

512K x 36

• Package

165-ball, 13mm x 15mm FBGA

MARKING

-3

-3.3

-4

-5

-6

-7.5

MT57W2MH8B

MT57W1MH18B

MT57W512H36B

VALID PART NUMBERS

PART NUMBER

MT57W2MH8BF-xx

MT57W1MH18BF-xx

MT57W512H36BF-xx

DESCRIPTION

2 Meg x 8, DDRIIb2 FBGA

1 Meg x 18, DDRIIb2 FBGA

512K x 36, DDRIIb2 FBGA

18Mb 1.8V V

, HSTL, DDRIIb2 SRAM

MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

‡

PRODUCTS

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