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MT55L512Y32FB-10

Description
ZBT SRAM, 512KX32, 7.5ns, CMOS, PBGA119, PLASTIC, MS-028BHA, BGA-119
Categorystorage    storage   
File Size498KB,46 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT55L512Y32FB-10 Overview

ZBT SRAM, 512KX32, 7.5ns, CMOS, PBGA119, PLASTIC, MS-028BHA, BGA-119

MT55L512Y32FB-10 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeBGA
package instructionPLASTIC, MS-028BHA, BGA-119
Contacts119
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B119
JESD-609 codee0
length22 mm
memory density16777216 bit
Memory IC TypeZBT SRAM
memory width32
Number of functions1
Number of terminals119
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA119,7X17,50
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height2.4 mm
Maximum standby current0.01 A
Minimum standby current3.14 V
Maximum slew rate0.525 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
18Mb
ZBT
®
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns and 12ns
Single +3.3V ±5%, or 2.5V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to eliminate
the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 4Mb, and 8Mb
ZBT SRAM
MT55L1MY18F, MT55V1MV18F,
MT55L512Y32F, MT55V512V32F,
MT55L512Y36F, MT55V512V36F
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
2.5V V
DD
, 2.5V I/O
6.6ns/8.8ns/113 MHz
7.5ns/10ns/100 MHz
9ns/12ns/83 MHz
3.3V V
DD
, 3.3V or 2.5V I/O
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP
165-pin FBGA
119-pin BGA
TQFP MARKING*
-8.8
-10
-12
-10
-11
-12
119-Pin BGA
2
MT55L1MY18F
MT55L512Y32F
MT55L512Y36F
MT55V1MV18F
MT55V512V32F
MT55V512V36F
T
F
B
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Part Number Example:
None
MT55L512Y32FT-11
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
1
©2001, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
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