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SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4 BIT UP/DOWN BINARY COUNTERS
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
•
•
•
•
•
Fully Synchronous Operation for Counting
and Programming
Internal Carry Look-Ahead Circuitry for
Fast Counting
Carry Output for n-Bit Cascading
Fully Independent Clock Circuit
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54ALS169B, SN54AS169A . . . J PACKAGE
SN74ALS169B, SN74AS169A . . . D OR N PACKAGE
(TOP VIEW)
U/D
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
description
These synchronous 4-bit up/down binary
presettable counters feature an internal carry
look-ahead circuitry for cascading in high-speed
counting applications. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes normally associated with
asynchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the
rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is,
they may be preset to either level. The load-input
circuitry allows loading with the carry-enable
output of cascaded counters. Because loading is
synchronous, setting up a low level at the load
(LOAD) input disables the counter and causes the
outputs to agree with the data inputs after the next
clock pulse.
SN54ALS169B, SN54AS169A . . . FK PACKAGE
(TOP VIEW)
A
B
NC
C
D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
CLK
U/D
NC
V
CC
RCO
Q
A
Q
B
NC
Q
C
Q
D
NC − No internal connection
Copyright
1994, Texas Instruments Incorporated
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs
are diode clamped to minimize transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)
that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
•
DALLAS, TEXAS 75265
ENP
GND
NC
LOAD
ENT
2−1
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4 BIT UP/DOWN BINARY COUNTERS
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
logic symbol
†
9
1
U/D
ENT
ENP
CLK
10
7
2
CTRDIV16
M1 [LOAD]
M2 [COUNT]
M3 [UP]
M4 [DOWN]
G5
G6
2,3,5,6+/C7
2,4,5,6 −
A
B
C
D
3
4
5
6
1, 7D
1
2
4
8
14
13
12
11
QA
QB
QC
QD
3,5CT=15
4,5CT=0
15
LOAD
RCO
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4 BIT UP/DOWN BINARY COUNTERS
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
logic diagram (positive logic)
LOAD
U/D
9
1
15
RCO
ENT
ENP
10
7
C1
CLK
A
2
3
1D
14
QA
C1
1D
B
4
13
QB
C1
1D
C
5
12
QC
C1
1D
D
6
11
QD
Pin numbers shown are for the D, J, and N packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
2−3
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4 BIT UP/DOWN BINARY COUNTERS
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD
A
B
C
D
CLK
U/D
ENP and ENT
QA
QB
QC
QD
RCO
13
14
15
0
1
2
2
Inhibit
2
1
0
15
14
13
Data
Inputs
Data
Outputs
Count Up
Load
Count Down
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, T
A
: SN54ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2−4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
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