HY5PS1G1631AFP-S5 datasheet, PDF

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HY5PS1G1631AFP-S5: DescriptionDDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84; Categorystorage storage; File Size4MB，36 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY5PS1G1631AFP-S5 Overview

DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84

HY5PS1G1631AFP-S5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	TFBGA, BGA92,9X21,32
Contacts	84
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B84
JESD-609 code	e1
length	17.5 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	84
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
organize	64MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA92,9X21,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.01 A
Maximum slew rate	0.48 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	11 mm

HY5PS1G1631AFP-S5 Preview

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1Gb DDR2 SDRAM

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

Revision Details

Rev.

0.1

0.2

0.3

0.4

0.5

Initial data sheet released

Typo corrected

Leakage current spec added and IDD value updated

Removed improper note in ODT DC spec

Added tDS/tDH(single ended strobe) parameter

History

Draft Date

Mar. 2006

May 2006

July 2006

Aug. 2006

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Key

Features

1.1.2 Ordering Information

1.1.3 Ordering Frequency

1.2 Pin configuration

1.3 Pin Description

2. Maximum DC ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditions

3.1 DC Operating Conditions

5.1.1 Recommended DC Operating Conditions(SSTL_1.8)

5.1.2 ODT DC Electrical Characteristics

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC Logic Level

3.2.5 Differential AC output parameters

3.3 Output Buffer Levels

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

3.3.3 OCD default

characteristics

3.4 IDD Specifications & Measurement Conditions

3.5 Input/Output Capacitance

4. AC Timing Specifications

5. Package Dimensions

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

•

VDD=1.8V

VDDQ=1.8V +/- 0.1V

All inputs and outputs are compatible with SSTL_18 interface

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

Differential Data Strobe (DQS, DQS)

Data outputs on DQS, DQS edges when read (edged DQ)

Data inputs on DQS centers when write(centered DQ)

On chip DLL align DQ, DQS and DQS transition with CK transition

DM mask write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising

edges of the clock

Programmable CAS latency 3, 4, 5 and 6 supported

Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

Programmable burst length 4/8 with both nibble sequential and interleave mode

Internal eight bank operations with single pulsed RAS

Auto refresh and self refresh supported

tRAS lockout supported

8K refresh cycles /64ms

JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16)

Full strength driver option controlled by EMRS

On Die Termination supported

Off Chip Driver Impedance Adjustment supported

Read Data Strobe supported (x8 only)

Self-Refresh High Temperature Entry

Ordering Information

Part No.

HY5PS1G431A(L)FP-X*

HY5PS1G831A(L)FP-X*

HY5PS1G1631A(L)FP-X*

Configuration Package

256Mx4

128Mx8

64Mx16

92 Ball

68 Ball

Operating Frequency

Grade

-E3

-C4

-Y5

-S5

tCK(ns)

3.75

2.5

tRCD

tRP

Unit

Clk

Note:

-X* is the speed bin, refer to the Operation Frequency table for complete Part No.

Rev. 0.5 / Aug 2006

HY5PS1G431A(L)FP

HY5PS1G831A(L)FP

HY5PS1G1631A(L)FP

1.2 Pin Configuration & Address Table

256Mx4 DDR2 Pin Configuration

(Top view: see balls through package)

VDD

VDDQ

VDDL

VSSQ

DQ1

VSSQ

VREF

CKE

VSS

VDDQ

DQ3

VSS

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

DQS

VSSQ

DQ0

VSSQ

A13

VDDQ

VDD

ODT

BA2

BA0

A10

VDD

VSS

VDD

A12

ROW AND COLUMN ADDRESS TABLE

ITEMS

# of Bank

Bank Address

Auto Precharge Flag

Row Address

Column Address

Page size

Rev. 0.5 / Aug 2006

256Mx4

BA0,BA1,BA2

A10/AP

A0 - A13

A0-A9, A11

1 KB

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HY5PS1G1631AFP-S5 Related Products

	HY5PS1G1631AFP-S5	HY5PS1G431AFP-S5	HY5PS1G1631ALFP-S5	HY5PS1G831AFP-S5	HY5PS1G431ALFP-S5	HY5PS1G831ALFP-S5
Description	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84	DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, FBGA-84	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA68, FBGA-68	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68, FBGA-68
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA, BGA92,9X21,32	TFBGA, BGA68,9X19,32	TFBGA, BGA92,9X21,32	TFBGA, BGA68,9X19,32	TFBGA, BGA68,9X19,32	TFBGA, BGA68,9X19,32
Contacts	84	68	84	68	68	68
Reach Compliance Code	compliant	unknown	compliant	compliant	compliant	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz	400 MHz	400 MHz	400 MHz	400 MHz	400 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	4,8	4,8	4,8	4,8	4,8	4,8
JESD-30 code	R-PBGA-B84	R-PBGA-B68	R-PBGA-B84	R-PBGA-B68	R-PBGA-B68	R-PBGA-B68
JESD-609 code	e1	e1	e1	e1	e1	e1
length	17.5 mm	17.5 mm	17.5 mm	17.5 mm	17.5 mm	17.5 mm
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	4	16	8	4	8
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	84	68	84	68	68	68
word count	67108864 words	268435456 words	67108864 words	134217728 words	268435456 words	134217728 words
character code	64000000	256000000	64000000	128000000	256000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	64MX16	256MX4	64MX16	128MX8	256MX4	128MX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA92,9X21,32	BGA68,9X19,32	BGA92,9X21,32	BGA68,9X19,32	BGA68,9X19,32	BGA68,9X19,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES
Continuous burst length	4,8	4,8	4,8	4,8	4,8	4,8
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	20	20
width	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm

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