®
IBM PowerPC
®
750FX RISC Microprocessor
Datasheet
(Support for 750FX Design Revision Level DD 2.X)
Version: 2.0
Preliminary
June 9, 2003
®
Copyright and Disclaimer
© Copyright International Business Machines Corporation 2003
All Rights Reserved
Printed in the United States of America June 2003
The following are trademarks of International Business Machines Corporation in the United States, or other countries,
or both.
IBM
IBM Logo
PowerPC
PowerPC Logo
PowerPC 750
PowerPC Architecture
RISCWatch
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction
could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not
affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied
license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu-
ment was obtained in specific environments, and is presented as an illustration. The results obtained in other operating
environments may vary.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
Note:
This document contains information on products in the sampling and/or initial production phases of
development. This information is subject to change without notice. Verify with your IBM field applications
engineer that you have the latest version of this document before finalizing a design.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be
liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY 12533-6351
The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at
http://www-3.ibm.com/chips/
Title_750FX_DS_DD2.X.fm.2.0
June 9, 2003
Preliminary
Preliminary
Datasheet
DD 2.X
PowerPC 750FX RISC Microprocessor
1. General Information .................................................................................................... 3
1.1 Features ............................................................................................................................................
1.2 Design Level Considerations and Features ......................................................................................
1.3 Processor Version Register ..............................................................................................................
1.4 Part Number Information ...................................................................................................................
3
5
5
6
2. Overview ...................................................................................................................... 7
2.1 Block Diagram ................................................................................................................................... 7
2.2 General Parameters .......................................................................................................................... 8
3. Electrical and Thermal Characteristics ..................................................................... 9
3.1 DC Electrical Characteristics ............................................................................................................. 9
3.2 Clock AC Specifications .................................................................................................................. 13
3.3 Spread Spectrum Clock Generator (SSCG) ................................................................................... 14
3.5 60x Bus Output AC Specifications .................................................................................................. 17
3.6 Alternate I/O Timing For 3.3V Bus .................................................................................................. 19
3.6.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 20
4. Dimensions and Signal Assignments ..................................................................... 22
4.1 Module Substrate Decoupling Voltage Assignments ...................................................................... 22
4.2 Package .......................................................................................................................................... 22
4.3 Microprocessor Ball Placement ....................................................................................................... 24
5. System Design Information ..................................................................................... 31
5.1 PLL Considerations .........................................................................................................................
5.1.1 Restrictions and Considerations for PLL Configuration .........................................................
5.1.1.1 Configuration Restriction on Frequency Transitions ......................................................
5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................
5.1.3 PLL Configuration ..................................................................................................................
5.2 PLL Power Supply Filtering .............................................................................................................
5.3 Decoupling Recommendations .......................................................................................................
5.4 Output Buffer DC Impedance ..........................................................................................................
5.4.1 Input-Output Usage ...............................................................................................................
5.5 Level Protection ..............................................................................................................................
5.6 64 or 32-Bit Data Bus Mode ............................................................................................................
5.7 IIO Voltage Mode Selection ............................................................................................................
5.8 Thermal Management .....................................................................................................................
5.8.1 Heat Sink Selection Example ................................................................................................
5.8.2 Internal Package Conduction ................................................................................................
5.8.3 Minimum Heat Sink Requirements ........................................................................................
5.8.4 Heat Sink Mounting ...............................................................................................................
5.8.5 Thermal Assist Unit ...............................................................................................................
5.8.6 Adhesives and Thermal Interface Materials ..........................................................................
5.8.7 Thermal Interface and Adhesive Vendors .............................................................................
5.8.8 Heat Sink Vendors .................................................................................................................
31
32
32
32
33
35
39
42
43
48
49
49
49
49
52
53
54
54
55
56
57
Revision Log ................................................................................................................ 59
750FX_DS_DD2.X_V2.02.fm.2.0
June 9, 2003
Page 1 of 63
Datasheet
DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
Page 2 of 63
750FX_DS_DD2.X_V2.02.fm.2.0
June 9, 2003
.
Preliminary
DD 2.X
PowerPC 750FX RISC Microprocessor
1. General Information
The IBM PowerPC
®
750FX RISC Microprocessor is a 32-bit implementation of the IBM PowerPC family of
reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and
electrical characteristics of the IBM PowerPC 750FX RISC Microprocessor Revision DD 2.X Single Chip
Modules (SCM). The IBM PowerPC 750FX RISC Microprocessor is also referred to as the 750FX throughout
this document.
1.1 Features
This section summarizes the features of the 750FX
implementation of the PowerPC Architecture™.
Major features of the 750FX include the following:
• Branch processing unit
– Four instructions fetched per clock
– One branch processed per cycle (plus
resolving two speculations)
– Up to one speculative stream in execution,
one additional speculative stream in fetch
– 512-entry branch history table (BHT) for
dynamic prediction
– 64-entry, 4-way set associative branch
target instruction cache (BTIC) for
eliminating branch delay slots
• Decode
– Register file access
– Forwarding control
– Partial instruction decode
• Load/store unit
– One cycle load or store cache access (byte,
half-word, word, double-word)
– Effective address generation
– Hits under miss (one outstanding miss)
– Single-cycle misaligned access within
double-word boundary
– Alignment, zero padding, sign extend for
integer register file
– Floating-point internal format conversion
(alignment, normalization)
– Sequencing for load/store multiples and
string operations
– Store gathering
– Cache and TLB instructions
– Big and little-endian byte addressing
supported
– Misaligned little-endian support in hardware
• Dispatch unit
– Full hardware detection of dependencies
(resolved in the execution units)
– Dispatch two instructions to six independent
units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, or floating-point)
– 4-stage pipeline: fetch, dispatch, execute,
and complete
– Serialization control (predispatch,
postdispatch, execution, serialization)
• Fixed-point units
– Fixed-point unit 1 (FXU1): multiply, divide,
shift, rotate, arithmetic, logical
– Fixed-point unit 2 (FXU2): shift, rotate,
arithmetic, logical
– Single-cycle arithmetic, shift, rotate, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
– Thirty-two 32-bit general purpose registers
• Floating-point unit
– Support for IEEE-754 standard single and
double-precision floating-point arithmetic
– Optimized for single-precision multiply/add
– Thirty-two, 64-bit floating point registers
– Enhanced reciprocal estimates
– 3-cycle latency, 1-cycle throughput,
single-precision multiply-add
– 3-cycle latency, 1-cycle throughput,
double-precision add
– 4-cycle latency, 2-cycle throughput,
double-precision multiply-add
– Hardware support for divide
– Hardware support for denormalized
numbers
– Time deterministic non-IEEE mode
• System unit
– Executes CR logical instructions and mis-
cellaneous system instructions
– Special register transfer instructions
1. General Information
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
Page 3 of 63
京公网安备 11010802033920号
EEWORLD
