MT41K128M16JT-125XIT:K datasheet, PDF

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MT41K128M16JT-125XIT:K: DescriptionDDR DRAM, 128MX16, CMOS, PBGA96, 8 X 14 MM, LEAD FREE, FBGA-96; Categorystorage storage; File Size3MB，212 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41K128M16JT-125XIT:K Overview

DDR DRAM, 128MX16, CMOS, PBGA96, 8 X 14 MM, LEAD FREE, FBGA-96

MT41K128M16JT-125XIT:K Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	8 X 14 MM, LEAD FREE, FBGA-96
Contacts	96
Reach Compliance Code	not_compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B96
JESD-609 code	e1
length	14 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	96
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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2Gb: x4, x8, x16 DDR3L SDRAM

Description

DDR3L SDRAM

MT41K512M4 – 64 Meg x 4 x 8 banks

MT41K256M8 – 32 Meg x 8 x 8 banks

MT41K128M16 – 16 Meg x 16 x 8 banks

Description

The 1.35V DDR3L SDRAM device is a low-voltage ver-

sion of the 1.5V DDR3 SDRAM device. Refer to the

DDR3 (1.5V) SDRAM data sheet specifications when

running in 1.5V compatible mode.

•

Automatic self refresh (ASR)

Write leveling

Multipurpose register

Output driver calibration

Options

• Configuration

– 512 Meg x 4

– 256 Meg x 8

– 128 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 10.5mm)

Rev. M, K

– 78-ball FBGA (9mm x 11.5mm)

Rev. D

• FBGA package (Pb-free) – x16

– 96-ball FBGA (9mm x 14mm)

Rev. D

– 96-ball FBGA (8mm x 14mm)

Rev. K

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.875ns @ CL = 7 (DDR3-1066)

• Operating temperature

– Commercial (0°C

≤

+95°C)

– Industrial (–40°C

≤

+95°C)

• Revision

Marking

512M4

256M8

128M16

Features

•

= V

DDQ

= 1.35V (1.283–1.45V)

Backward-compatible to V

= V

DDQ

= 1.5V ±0.075V

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

Programmable CAS (READ) latency (CL)

Programmable posted CAS additive latency (AL)

Programmable CAS (WRITE) latency (CWL)

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C

– 32ms at +85°C to +95°C

Self refresh temperature (SRT)

-107

-125

-15E

-187E

None

:D/ :M / :K

•

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2, 3

-125

1, 2

-15E

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-107).

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. K 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

2Gb: x4, x8, x16 DDR3L SDRAM

Description

Contents

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature ............................................................................................................................... 12

General Notes ............................................................................................................................................ 12

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 22

Electrical Specifications .................................................................................................................................. 26

Absolute Ratings ......................................................................................................................................... 26

Input/Output Capacitance .......................................................................................................................... 27

Thermal Characteristics .................................................................................................................................. 28

Electrical Specifications – I

Specifications and Conditions ............................................................................ 30

Electrical Characteristics – I

Specifications .................................................................................................. 41

Electrical Specifications – DC and AC .............................................................................................................. 44

DC Operating Conditions ........................................................................................................................... 44

Input Operating Conditions ........................................................................................................................ 45

DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 49

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 52

DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 54

ODT Characteristics ....................................................................................................................................... 55

1.35V ODT Resistors ................................................................................................................................... 56

ODT Sensitivity .......................................................................................................................................... 57

ODT Timing Definitions ............................................................................................................................. 57

Output Driver Impedance ............................................................................................................................... 61

34 Ohm Output Driver Impedance .............................................................................................................. 62

DDR3L 34 Ohm Driver ................................................................................................................................ 63

DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 64

DDR3L Alternative 40 Ohm Driver ............................................................................................................... 65

DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 65

Output Characteristics and Operating Conditions ............................................................................................ 67

Reference Output Load ............................................................................................................................... 70

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 70

Slew Rate Definitions for Differential Output Signals .................................................................................... 72

Speed Bin Tables ............................................................................................................................................ 73

Electrical Characteristics and AC Operating Conditions ................................................................................... 77

Command and Address Setup, Hold, and Derating ........................................................................................... 97

Data Setup, Hold, and Derating ...................................................................................................................... 104

Commands – Truth Tables ............................................................................................................................. 112

Commands ................................................................................................................................................... 115

DESELECT ................................................................................................................................................ 115

NO OPERATION ........................................................................................................................................ 115

ZQ CALIBRATION LONG ........................................................................................................................... 115

ZQ CALIBRATION SHORT .......................................................................................................................... 115

ACTIVATE ................................................................................................................................................. 115

READ ........................................................................................................................................................ 115

WRITE ...................................................................................................................................................... 116

PRECHARGE ............................................................................................................................................. 117

REFRESH .................................................................................................................................................. 117

SELF REFRESH .......................................................................................................................................... 118

DLL Disable Mode ..................................................................................................................................... 119

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. K 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x4, x8, x16 DDR3L SDRAM

Description

Input Clock Frequency Change ...................................................................................................................... 123

Write Leveling ............................................................................................................................................... 125

Write Leveling Procedure ........................................................................................................................... 127

Write Leveling Mode Exit Procedure ........................................................................................................... 129

Initialization ................................................................................................................................................. 130

Voltage Initialization / Change ....................................................................................................................... 132

Voltage Switching ............................................................................................................................... 133

Mode Registers .............................................................................................................................................. 134

Mode Register 0 (MR0) ................................................................................................................................... 135

Burst Length ............................................................................................................................................. 135

Burst Type ................................................................................................................................................. 136

DLL RESET ................................................................................................................................................ 137

Write Recovery .......................................................................................................................................... 137

Precharge Power-Down (Precharge PD) ...................................................................................................... 138

CAS Latency (CL) ....................................................................................................................................... 138

Mode Register 1 (MR1) ................................................................................................................................... 139

DLL Enable/DLL Disable ........................................................................................................................... 139

Output Drive Strength ............................................................................................................................... 140

OUTPUT ENABLE/DISABLE ...................................................................................................................... 140

TDQS Enable ............................................................................................................................................. 140

On-Die Termination .................................................................................................................................. 141

WRITE LEVELING ..................................................................................................................................... 141

POSTED CAS ADDITIVE Latency ................................................................................................................ 141

Mode Register 2 (MR2) ................................................................................................................................... 142

CAS Write Latency (CWL) ........................................................................................................................... 143

AUTO SELF REFRESH (ASR) ....................................................................................................................... 143

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144

SRT vs. ASR ............................................................................................................................................... 144

DYNAMIC ODT ......................................................................................................................................... 144

Mode Register 3 (MR3) ................................................................................................................................... 145

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 145

MPR Functional Description ...................................................................................................................... 146

MPR Register Address Definitions and Bursting Order ................................................................................. 147

MPR Read Predefined Pattern .................................................................................................................... 153

MODE REGISTER SET (MRS) Command ........................................................................................................ 153

ZQ CALIBRATION Operation ......................................................................................................................... 154

ACTIVATE Operation ..................................................................................................................................... 155

READ Operation ............................................................................................................................................ 157

WRITE Operation .......................................................................................................................................... 168

DQ Input Timing ....................................................................................................................................... 176

PRECHARGE Operation ................................................................................................................................. 178

SELF REFRESH Operation .............................................................................................................................. 178

Extended Temperature Usage ........................................................................................................................ 180

Power-Down Mode ........................................................................................................................................ 181

RESET Operation ........................................................................................................................................... 189

On-Die Termination (ODT) ............................................................................................................................ 191

Functional Representation of ODT ............................................................................................................. 191

Nominal ODT ............................................................................................................................................ 191

Dynamic ODT ............................................................................................................................................... 193

Dynamic ODT Special Use Case ................................................................................................................. 193

Functional Description .............................................................................................................................. 193

Synchronous ODT Mode ................................................................................................................................ 199

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. K 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT41K128M16JT-125XIT:K Related Products

	MT41K128M16JT-125XIT:K	MT41K256M8DA-125IT:KTR	MT41K128M16JT-125XIT:KT
Description	DDR DRAM, 128MX16, CMOS, PBGA96, 8 X 14 MM, LEAD FREE, FBGA-96	DDR DRAM, 256MX8, CMOS, PBGA78, 8 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM,
Reach Compliance Code	not_compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
Maker	Micron Technology	Micron Technology	-
package instruction	8 X 14 MM, LEAD FREE, FBGA-96	TFBGA,	-
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	-
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-
JESD-30 code	R-PBGA-B96	R-PBGA-B78	-
length	14 mm	10.5 mm	-
memory density	2147483648 bit	2147483648 bit	-
memory width	16	8	-
Number of functions	1	1	-
Number of ports	1	1	-
Number of terminals	96	78	-
word count	134217728 words	268435456 words	-
character code	128000000	256000000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-
organize	128MX16	256MX8	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TFBGA	TFBGA	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	-
Maximum seat height	1.2 mm	1.2 mm	-
self refresh	YES	YES	-
Maximum supply voltage (Vsup)	1.45 V	1.45 V	-
Minimum supply voltage (Vsup)	1.283 V	1.283 V	-
Nominal supply voltage (Vsup)	1.35 V	1.35 V	-
surface mount	YES	YES	-
technology	CMOS	CMOS	-
Terminal form	BALL	BALL	-
Terminal pitch	0.8 mm	0.8 mm	-
Terminal location	BOTTOM	BOTTOM	-
width	8 mm	8 mm	-

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