YDA144
D- 4N
STEREO 2.1W Non-Clip DIGITAL AUDIO POWER AMPLIFIER
■Overview
YDA144 (D-4N) is a digital audio power amplifier IC with maximum output of 2.1W (R
L
=4Ω)×2ch.
YDA144 has a “Pure Pulse Direct Speaker Drive Circuit” which directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, and realizes the highest standard low distortion rate characteristics
and low noise characteristics among digital amplifier ICs for mobile use.
In addition, circuit design with fewer external parts can be made depend on the condition of use because corresponds to
filter less.
The YDA144 features Yamaha original non-clip output control function which detects output signal clip due to the over
level input signal and suppress the output signal clip automatically. Also the non-clip output control function can adapt
the output clip caused by power supply voltage down with battery. This is the difference from the traditional AGC (Auto
Gain Control) or ALC (Auto Level Control) circuit. Attack time and release time can be freely set by external resistances
or capacitances.
The independent power-down function for L channel and R channel minimizes consumption current at standby. As for
protection function, overcurrent protection function for speaker output terminal, overtemperatue protection function for
inside of the device, and low supply voltage malfunction preventing function are prepared.
■Features
・Maximum
output
2.1 W×2ch (V
DDP
=V
DDA
=5.0V, R
L
=4Ω, THD+N=10%)
0.75 W×2ch (V
DDP
=V
DDA
=3.6V, R
L
=8Ω, THD+N=10%)
・Distortion
Rate (THD+N)
0.03 % (V
DDP
=V
DDA
=3.6V, R
L
=8Ω, Po=0.4W, 1kHz)
・Residual
Noise
40µVrms (V
DDP
=V
DDA
=3.6V, Av=12dB)
・Efficiency
84 % (V
DDP
=V
DDA
=3.6V, R
L
=8Ω, Po=600mW)
78 % (V
DDP
=V
DDA
=3.6V, R
L
=8Ω, Po=100mW)
・S/N
Ratio
95dB (V
DDP
=V
DDA
=3.6V, Av=12dB)
・Channel
separation
95dB (V
DDP
=V
DDA
=3.6V, R
L
=8Ω, Av=18dB, 1kHz)
・Over-current
Protection function
・Thermal
Protection function
・Low
voltage Malfunction Prevention function
・
2ch independent power-down control function
・Power-down
High speed Recovery function
・Package
Lead-free 16-ball WLCSP (YDA144-WZ)
Lead-free 20-pin QFN (YDA144-QZ)
YDA144 CATALOG
CATALOG No.:LSI-4DA144A30
2006.11
YDA144
■Terminal
configuration
<16-ball WLCSP Top View>
<20-pin QFN Top View>
2
YDA144
■Terminal
function
・WLCSP16
No.
Name
I/O
Protection circuit composition
Function
A1
A
INL+
PN
Positive input terminal (differential +) Lch
A2
Power
PVDD
-
Power supply for output
A3
O
OUTL+
-
Positive output terminal (differential +) Lch
A4
O
OUTL-
-
Negative output terminal (differential -) Lch
B1
A
INL-
PN
Negative input terminal (differential -) Lch
B2
I/O
NCRC
PN
Non-Clip control terminal
B3
I
/SDR
N
Shut-down terminal for Rch
B4
I
/SDL
N
Shut-down terminal for Lch
C1
A
INR-
PN
Negative input terminal (differential -) Rch
C2
I
G0
N
Gain setting terminal
C3
GND
AGND
-
GND for analog circuits
C4
GND
PGND
-
GND for output
D1
A
INR+
PN
Positive input terminal (differential +) Rch
D2
Power
AVDD
-
Power supply for analog circuits
D3
O
OUTR+
-
Positive output terminal (differential +) Rch
D4
O
OUTR-
-
Negative output terminal (differential -) Rch
(Note) I: Input terminal O: Output terminal A: Analog terminal
When a voltage that is bigger than the AVDD potential is impressed to the terminal of PN (protection circuit is
composed of PMOS and NMOS), the leakage current flows through the protection circuit of PMOS.
・QFN20
No.
Name
I/O
Protection circuit composition
Function
1
I/O
Non-Clip control terminal
NCRC
PN
2
O
Positive output terminal (differential +) Lch
OUTL+
-
3
Power
Power supply for output
PVDD
-
4
GND
GND for output
PGND
-
5
O
Negative output terminal (differential -) Lch
OUTL-
-
6
-
Non connection or connect to AGND
NC
-
7
I
Shut-down terminal for Lch
/SDL
N
8
I
Shut-down terminal for Rch
/SDR
N
9
Power
Power supply for analog circuits
AVDD
-
10
-
Non connection or connect to AGND
NC
-
11
O
Negative output terminal (differential -) Rch
OUTR-
-
12
GND
GND for output
PGND
-
13
Power
Power supply for output
PVDD
-
14
O
Positive output terminal (differential +) Rch
OUTR+
-
15
I
Gain setting terminal
G0
N
16
A
Positive input terminal (differential +) Rch
INR+
PN
17
A
Negative output terminal (differential -) Rch
INR-
PN
18
GND
GND for analog circuits
AGND
-
19
A
Negative input terminal (differential -) Lch
INL-
PN
20
A
Positive input terminal (differential +) Lch
INL+
PN
(Note) I: Input terminal O: Output terminal A: Analog terminal
When a voltage that is bigger than the AVDD potential is impressed to the terminal of PN (protection circuit is
composed of PMOS and NMOS), the leakage current flows through the protection circuit of PMOS.
3
YDA144
■Block
diagram
4
YDA144
■Description
of operating functions
●Digital
Amplifier Function
YDA144 has digital amplifiers with analog and digital input, PWM pulse output, Maximum output of 2.1W(R
L
=4Ω)×2ch.
Distortion of PWM pulse output signal and noise of the signal is reduced by adopting “Pure Pulse Direct Speaker Drive
Circuit”
In addition, YDA144 has been designed so that high-efficiency can be maintained within an average power range (100mW
or so) that is used for mobile terminal.
First Stage Amplifier Gain Setting Function
G0 terminal can set the Gain of YDA144. When Non-Clip function is disabled, the relation between G0 terminal setting and
Gain is as follows.
Digital Amplifier Gain Setting
G0
Gain
Input Impedance(Z
IN
)
L
12dB
44kΩ
H
18dB
28kΩ
Note） H and L indicates logic High and logic Low, respectively.
Input Lch differential input signals to INL+ terminal and INL- terminal through DC-cut capacitors (C
IN
). For single ended
operation, input the signal to INL+ pin through the DC-cut capacitor (C
IN
). At this time, INL- pin must be connected to
AVSS pin through a capacitor (C
REF
: same value as C
IN
). As with Lch, connect input signals to Rch.
＜Differential input＞
＜Single input＞
In addition, positive (+) and negative (-) sides of differential input pins (INL+ and INL-, or INR+ and INR-), input pins of
the unused channel side, should be connected to each other and connected to AVSS through a capacitor.
Use a capacitor with the same capacitance (0.1µF) as that of a DC-cut capacitor in the channel side being used.
＜Input terminal processing of unused channel side＞
The lower cut-off frequency (fc) can be found from DC-cut capacitor (C
IN
) and input impedance (Z
IN
) as shown below.
fc=1/(2*π*Z
IN
*C
IN
)
In order to reduce pop-noise, impedance in the differential input signal source is arranged. And, DC-cut capacitor (C
IN
)
should be 0.1µF or less.
5
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