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Datasheet> All Categories > Programmable logic devices> Programmable logic> PA7128P-15
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PA7128P-15

Description
EE PLD, 15ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
CategoryProgrammable logic devices    Programmable logic   
File Size329KB，6 Pages
ManufacturerIntegrated Circuit Systems（IDT ）
Download Datasheet Parametric Compare View All

PA7128P-15 Overview

EE PLD, 15ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28

PA7128P-15 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntegrated Circuit Systems（IDT ）
Parts packaging codeDIP
package instructionDIP, DIP28,.3
Contacts28
Reach Compliance Codeunknown
Other features12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency83.3 MHz
JESD-30 codeR-PDIP-T28
JESD-609 codee0
Dedicated input times12
Number of I/O lines12
Number of entries26
Output times12
Number of terminals28
Maximum operating temperature70 °C
Minimum operating temperature
organize12 DEDICATED INPUTS, 12 I/O
Output functionCOMBINATORIAL
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Programmable logic typeEE PLD
propagation delay15 ns
Certification statusNot Qualified
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL

PA7128P-15 Preview

Commercial/
Industrial
PA7128
PA7128 PEEL
TM
Array
Programmable Electrically Erasable Logic Array
Features
s
CMOS Electrically Erasable Technology
−
Reprogrammable in 28-pin DIP SOIC and PLCC
,
packages
Versatile Logic Array Architecture
−
12 I/Os, 14 inputs, 36 registers/latches
−
Up to 36 logic cell output functions
−
PLA structure with true product-term sharing
−
Logic functions and registers can be I/O-buried
Flexible Logic Cell
−
Up to 3 output functions per logic cell
−
D,T and JK registers with special features
−
Independent or global clocks, resets, presets, clock
polarity and output enables
−
Sum-of-products logic for output enables
High-Speed Commercial and Industrial Versions
s
−
As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f
MAX
)
−
Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85 °C temperatures
Ideal for Combinatorial, Synchronous and Asyn-
chronous Logic Applications
−
Integration of multiple PLDs and random logic
−
Buried counters, complex state-machines
−
Comparitors, decoders, other wide-gate functions
Development and Programmer Support
−
ICT PLACE Development Software
−
Fitters for ABEL, CUPL and other software
−
Programming support by ICT PDS-3 and other popu-
lar third-party programmers.
2
s
s
s
s
General Description
The PA7128 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7128 offers a versatile
logic array architecture with 12 I/O pins, 14 input pins and
36 registers/latches (12 buried logic cells, 12 input regis-
ters/latches, 12 buried I/O registers/latches). Its logic array
implements 50 sum-of-products logic functions that share
64 product terms. The PA7128’s logic and I/O cells (LCCs,
IOCs) are extremely flexible offering up to three output
functions per cell (a total of 36 for all 12 logic cells). Cells
are configurable as D, T and JK registers with independent
or global clocks, resets, presets, clock polarity and other
special features, making the PA7128 suitable for a variety of
combinatorial, synchronous and asynchronous logic appli-
cations. The PA7128 offers pin compatibility and super-set
functionality to popular 28-pin PLDs, such as the 26V12.
Thus, designs that exceed the architectures of such
devices can be expanded upon. The PA7128 supports
speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (f
MAX
)
at moderate power consumption 105mA (75mA typical).
Packaging includes 28-pin DIP SOIC and PLCC (see Fig-
,
ure 1). Development and programming support for the
PA7128 is provided by ICT and popular third-party develop-
ment tool manufacturers.
Figure 1. Pin Configuration
Figure 2. Block Diagram
1/CLK
1
Global Cells
Input Cells
I/O Cells
1CLK2
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
Logic Control Cells
I/O
I/O
1/CLK1
I
I
I
I
I
Vcc
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
1
1
1
1
1
Vcc
PLCC
1
1
1
1
1
1
DIP
1
SOIC
1 of 6
PA7128
This device has been designed and tested for the recom-
mended operating conditions. Proper operation outside of
these levels is not guaranteed. Exposure to absolute maxi-
mum ratings may cause permanent damage
Table 2. Absolute Maximum Ratings
Symbol
V
CC
V
I
, V
O
I
O
T
ST
T
LT
Parameter
Supply Voltage
Voltage Applied to Any Pin
Output Current
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Relative to Ground
1
Per pin (I
OL
, I
OH
)
Ratings
-0.5 to + 7.0
-0.5 to V
CC
+ 0.6
±25
-65 to + 150
Unit
V
V
mA
°C
°C
Soldering 10 seconds
+300
Table 3. Operating Ranges
Symbol
V
CC
Parameter
Supply Voltage
Conditions
Commercial
Industrial
Commercial
Industrial
See Note 2
See Note 2
See Note 2
Min
4.75
4.5
0
-40
Max
5.25
5.5
+70
+85
20
20
250
Unit
V
T
A
T
R
T
F
T
RVCC
Ambient Temperature
Clock Rise Time
Clock Fall Time
V
CC
Rise Time
°C
ns
ns
ms
Table 4. D.C. Electrical Characteristics
Over the recommended operating conditions
Symbol
V
OH
V
OHC
V
OL
V
OLC
V
IH
V
IL
I
IL
I
OZ
I
SC
Parameter
Output HIGH Voltage - TTL
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
Output LOW Voltage - CMOS
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Output Short Circuit Current
4
Conditions
V
CC
= Min, I
OH
= -4.0mA
V
CC
= Min, I
OH
= -10µA
V
CC
= Min, I
OL
= 16mA
V
CC
= Min, I
OL
= -10µA
Min
2.4
V
CC
- 0.3
Max
Unit
V
V
0.5
0.15
2.0
-0.3
V
CC
+ 0.3
0.8
±10
±10
-30
-15
-20
I-20
75 (typ.)
19
-120
105
105
115
6
12
V
V
V
V
µA
µA
mA
V
CC
= Max, GND
≤
V
IN
≤
V
CC
I/O = High-Z, GND
≤
V
O
≤
V
CC
V
CC
= 5V, V
O
= 0.5V, T
A
= 25°C
V
IN
= 0V or V
CC
3,11
f = 25MHz
All outputs
disabled
4
ICC
11
V
CC
Current
mA
C
IN
7
C
OUT
7
Input Capacitance
5
Output Capacitance
5
T
A
= 25°C, V
CC
= 5.0V
@ f = 1 MHz
pF
pF
2 of 6
PA7128
A.C Electrical Characteristics Combinatorial
-15
Symbol
t
PDI
t
PDX
t
IA
t
AL
t
LC
t
LO
t
OD
, t
OE
t
OX
Parameter
6,12
Propagation delay Internal (t
AL + tLC)
Propagation delay External (t
IA
+ t
AL
+t
LC
+ t
LO
)
Input or I/O pin to array input
Array input to LCC
LCC input to LCC output
10
LCC output to output pin
Output Disable, Enable from LCC output
7
Output Disable, Enable from input pin
7
Min
Max
9
15
2
8
1
4
4
15
-20 / I -20
Min
Max
12
20
3
10
2
5
5
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
2
Combinatorial Timing - Waveforms and Block Diagram
3 of 6
PA7128
A.C. Electrical Characteristics Sequential
-20
Symbol
t
SCI
t
SCX
t
COI
t
COX
t
HX
t
SK
t
AK
t
HK
t
SI
t
HI
t
PK
t
SPI
t
HPI
t
SD
t
HD
t
SDP
t
HDP
t
CK
t
CW
f
MAX
1
f
MAX
2
f
MAX
3
f
MAX
4
f
TGL
t
PR
t
ST
t
AW
t
RT
t
RTV
t
RTC
t
RW
t
RESET
Parameter
6,12
Internal set-up to system clock
8
- LCC
14
(t
AL
+ t
SK
+ t
LC
- t
CK
)
Input
16
(EXT.) set-up to system clock, - LCC (t
IA +
t
SCI)
System-clock to Array Int. - LCC/IOC/INC
14
(t
CK
+t
LC
)
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
Input hold time from system clock - LCC
LCC Input set-up to async. clock
13
- LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC
14
(t
SK
- t
CK
)
Input hold time from system clock - IOC/INC
14
(t
SK
- t
CK
)
Array input to IOC PCLK clock
Input set-up to PCLK clock
17
- IOC/INC (t
SK
-t
PK
-t
IA
)
Input hold from PCLK clock
17
- IOC/INC (t
PK
+t
IA
-t
SK
)
Input set-up to system clock - IOC/INC Sum-D
15
(t
IA
+ t
AL
+ t
LC
+ t
SK
- t
CK
)
Input hold time from system clock - IOC Sum-D
Input set-up to PCLK clock
(t
IA
+ t
AL
+ t
LC
+ t
SK
- t
PK
) - IOC Sum-D
Input hold time from PCLK clock - IOC Sum-D
System-clock delay to LCC/IOCINC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
LCC presents/reset to LCC output
Input to Global Cell present/reset (
tIA
+ t
AL
+ t
PR
)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (t
RT
+ t
RTV
)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state
2
Min
5
7
Max
-20 / I-20
Min
Max
7
10
Unit
ns
ns
7
11
0
2
1
4
0
4
6
0
6
7
0
7
0
6
6
83.3
71.4
62.5
55.5
83.3
1
11
8
7
1
8
10
5
10
8
7
0
8
10
0
10
0
0
2
1
4
0
5
9
14
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
62.5
52.6
47.6
41.6
71.4
2
15
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
9
2
11
ns
ns
ns
ns
5
µs
4 of 6
PA7128
Sequential Timing - Waveforms and Block Diagram
2
Notes:
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for
periods less than 20ns.
2. Test points for Clock and V
CC
in t
R
, t
F
, t
CL
, t
CH
, and t
RESET
are referenced
at 10% and 90% levels.
3. I/O pins are 0V or V
CC
.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
7. t
OE
is measured from input transition to V
REF
0.1V (See test loads at
end of Section 6 for V
REF
value). t
OD
is measured from input transition to
V
OH
-0.1V or V
OL
+0.1V.
8. “System-clock” refers to pin 1 or pin 28 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC” term indicates that the tim-
ing parameter is applied to both the LCC and IOC registers. The “LCC/
IOC/INC” term indicates that the timing parameter is applied to the
LCC, IOC and INC registers.
15. This refers to the Sum-D gate routed to the IOC register for an addi-
tional buried register
16. The term “Input” without any reference to another term refers to an
(external) input pin.
17. The parameter t
SPI
indicates that the PCLK signal to the IOC register is
always slower than the data from the pin or input by the absolute value
of (t
SK
-t
PK
-t
IA
). This means that no set-up time for the data from the
pin or input is required, i.e. the external data and clock can be sent to
the device simultaneously. Additionally, the data from the pin must
remain stable for t
HPI
time, i.e. to wait for the PCLK signal to arrive at
the IOC register.
18. Typical (typ) I
CC
is measured at T
A
=25
o
C, Freq = 25MHz, V
CC
=5V.
5 of 6
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PA7128P-15 Related Products

PA7128P-15 PA7128P-20 PA7128PI-20
Description EE PLD, 15ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 EE PLD, 20ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 EE PLD, 20ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
Is it Rohs certified? incompatible incompatible incompatible
Maker Integrated Circuit Systems（IDT ） Integrated Circuit Systems（IDT ） Integrated Circuit Systems（IDT ）
Parts packaging code DIP DIP DIP
package instruction DIP, DIP28,.3 DIP, DIP28,.3 DIP, DIP28,.3
Contacts 28 28 28
Reach Compliance Code unknown unknown unknown
Other features 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency 83.3 MHz 71.4 MHz 71.4 MHz
JESD-30 code R-PDIP-T28 R-PDIP-T28 R-PDIP-T28
JESD-609 code e0 e0 e0
Dedicated input times 12 12 12
Number of I/O lines 12 12 12
Number of entries 26 26 26
Output times 12 12 12
Number of terminals 28 28 28
Maximum operating temperature 70 °C 70 °C 85 °C
organize 12 DEDICATED INPUTS, 12 I/O 12 DEDICATED INPUTS, 12 I/O 12 DEDICATED INPUTS, 12 I/O
Output function COMBINATORIAL COMBINATORIAL COMBINATORIAL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP DIP DIP
Encapsulate equivalent code DIP28,.3 DIP28,.3 DIP28,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE IN-LINE
power supply 5 V 5 V 5 V
Programmable logic type EE PLD EE PLD EE PLD
propagation delay 15 ns 20 ns 20 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum supply voltage 5.25 V 5.25 V 5.5 V
Minimum supply voltage 4.75 V 4.75 V 4.5 V
Nominal supply voltage 5 V 5 V 5 V
surface mount NO NO NO
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 2.54 mm 2.54 mm
Terminal location DUAL DUAL DUAL

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