PEEL20V8J-15 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> PEEL20V8J-15

PEEL20V8J-15: DescriptionEE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size198KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

Download Datasheet Parametric Compare View All

PEEL20V8J-15 Overview

EE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28

PEEL20V8J-15 Parametric

Parameter Name	Attribute value
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	unknown
maximum clock frequency	45.5 MHz
JESD-30 code	S-PQCC-J28
length	11.5062 mm
Dedicated input times	12
Number of I/O lines	8
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.5062 mm

PEEL20V8J-15 Preview

Preliminary

Commercial

PEEL

™

20V8 -15/-25

CMOS Programmable Electrically Erasable Logic Device

Features

Compatible with Popular 20V8 Devices



20V8 socket and function compatible



Programs with standard 20V8 JEDEC file



24-pin DIP/SOIC, 28-pin PLCC packages

CMOS Electrically Erasable Technology



Superior factory testing



Reprogrammable in plastic package



Reduces retrofit and development costs

Application Versatility



Replaces random logic



Super-sets standard 24-pin PLDs (PALs)

Icc



20mA typical Icc

Development/Programmer Support



Third party software and programmers



ICT PLACE Development Software and

PDS-3 programmer



Automatic programmer translation and

JEDEC file translation software available

for the most popular PAL devices

General Description

The PEEL20V8 is a Programmable Electrically

Erasable Logic (PEEL) device providing an attrac-

tive alternative to ordinary PLDs. The PEEL20V8

offers the performance, flexibility, ease-of-design

and production practicality needed by logic design-

ers today. The PEEL20V8 is available in 24-pin DIP

and PLCC packages (see Figure 1) with speeds

ranging from 15ns to 25ns and power consumption

as low as 20mA. EE-reprogrammability provides the

convenience of instant reprogramming for develop-

ment and a reusable production inventory minimiz-

ing the impact of programming changes or errors.

EE-reprogrammability also improves factory test-

ability, thus ensuring the highest quality possible.

Pin Configuration

(Figure 1)

I/CLK

The PEEL20V8 is socket and function compatible

with other 20V8 devices. Its architecture allows it to

replace many standard 24-pin PALs. See Figure 2.

ICT’s PEEL20V8 can be programmed with any ex-

isting 20V8 JEDEC file. Some programmers also

allow the PEEL20V8 to be programmed directly

from PAL 20L8, 20R4, 20R6 and 20R8 JEDEC files.

Additional development and programming support for

the PEEL20V8 is provided by popular third-party pro-

grammers and development software. ICT also offers

free PLACE development software and a low-cost

development system (PDS-3).

Block Diagram

(Figure 2)

CLK

PEEL

"AND"

ARRAY

64 TERMS

40 INPUTS

MACRO

CELL

DIP

I/OE

I/O

PLCC

3 - 25

PEEL

™

20V8

Functional Description

The PEEL20V8 implements logic functions as sum-

of-products expressions in a programmable-

AND/fixed-OR logic array. User-defined functions

are created by programming the connections of in-

put signals into the array. User-configurable output

structures in the form of macrocells further increase

logic flexibility.

Architecture Overview

The PEEL20V8 features fourteen dedicated input

pins and eight I/O pins, which allow a total of up to

20 inputs and 8 outputs for creating logic functions.

At the core of the device is a programmable electri-

cally-erasable AND array which drives a fixed OR

array. With this structure the PEEL20V8 can imple-

ment up to 8 sum-of-products logic expressions.

Associated with each of the eight OR functions is a

macrocell which can be independently programmed

to one of up to four different basic configurations:

active-high or active-low registered logic output

(with registered feedback) or active-high or active-

low combinatorial logic output (with I/O pin feedback).

Three different device modes: Simple, Complex and

Registered, support various user configurations. In

Simple mode, a macrocell can be configured for

combinatorial function with the output buffer perma-

nently enabled, or the output buffer can be disabled

and the I/O pin used as a dedicated input. In Com-

plex mode a macrocell is configured for combinato-

rial function with the output buffer enable controlled

by a product term. In Registered mode, a macrocell

can be configured for registered operation with the

directly from pins, or can be configured for combi-

natorial function with the output buffer enable con-

trolled by a product term. In most cases, the device

mode is set automatically by the development soft-

ware based on the features specified in the design.

The three device modes support designs created

explicitly for the PEEL20V8, as well as designs cre-

ated originally for popular PAL devices such as the

20R4, 20R8 and 20L8. Table 1 shows the device

mode used to emulate the various PALs. Design

conversion into the 20V8 is accommodated by sev-

eral programmers which can read the original PAL

JEDEC file and automatically program the 20V8 to

perform the same function.

AND/OR Logic Array

The programmable AND array of the PEEL20V8 is

formed by input lines intersecting product terms. The

input lines and product terms are used as follows:

40 input lines:

24 input lines carry the true and complement of

the signals applied to the 12 dedicated input pins

16 additional lines carry the true and complement

of 8 macrocell feedback signals or inputs from I/O

pins or the clock/OE pins

64 product terms:

56 product terms (arranged in 8 groups of 7) form

sum-of-product functions for macrocell combina-

torial or registered logic

8 product terms (arranged 1 per macrocell) add

an additional product term for macrocell sum-of-

products functions or I/O pin output enable control

At each input-line/product-term intersection there is

an EEPROM memory cell which determines

whether or not there is a logical connection at that

intersection. Each product term is essentially a 32-

input AND gate. A product term which is connected

to both the true and complement of an input signal

will always be FALSE and thus will not affect the OR

function that it drives. When all the connections on

a product term are opened, that term will always be

TRUE.

When programming the PEEL20V8, the device pro-

grammer first performs a bulk erase to remove the

previous pattern. The erase cycle opens every logi-

cal connection in the array. The device is configured

to perform the user-defined function by program-

ming selected connections in the AND array. (Note

that PEEL device programmers automatically pro-

gram at least one pair of complementary inputs on

unused product terms so that they will have no

effect on the output function.)

Table 1. PEEL20V8/PAL Device Compatibility

PAL Architecture

PEEL20V8

Compatibility

Device Mode

14H8

14L8

14P8

16H6

16L6

16P6

18H4

18L4

18P4

20H2

20L2

20P2

20H8

20L8

20P8

20R4

20R6

Simple

Complex

Registered

3 - 26

PEEL

™

20V8

20R8

20RP4

20RP6

20RP8

Registered

Programmable Macrocell

The macrocell provides complete control over the

architecture of each output. The ability to configure

each output independently permits users to tailor

the configuration of the PEEL20V8 to the precise

requirements of their designs.

Macrocell Architecture

Each macrocell consists of an OR function, a D-type

flip-flop, an output polarity selector and a program-

mable feedback path. Four EEPROM architecture

bits MS0, MS1, OP and RC control the configuration

of each macrocell. Bits MS0 and MS1 are global,

and select between Simple, Complex and Regis-

tered mode for the whole device. Bits OP and RC

are local for each macrocell; bit OP controls the

output polarity and bit RC selects between regis-

tered and combinatorial operation and also speci-

fies the feedback path. Table 2 shows the architec-

ture bit settings for each possible configuration.

Equivalent circuits for the possible macrocell con-

figurations are illustrated in Figures 3, 4 and 5.

When creating a PEEL device design, the desired

macrocell configuration generally is specified explic-

itly in the design file. When the design is assembled

or compiled, the macrocell configuration bits are

defined in the last lines of the JEDEC programming

file.

Simple Mode

In Simple mode, all eight product terms feed the OR

array which can generate a purely combinatorial

function for the output pin. The programmable out-

put polarity selector allows active-high or active-low

logic, eliminating the need for external inverters.

For output functions, the buffer can be permanently

enabled. Feedback into the array is available on all

macrocell I/O pins, except for DIP/SOIC pins 18 and

19 (PLCC pins 21 and 23). Figure 6 shows the logic

array of the PEEL20V8 configured in Simple mode.

Simple Mode

Active Low Output

VCC

Simple Mode

Active High Output

VCC

Simple Mode

I/O Pin Input

Figure 3. Macrocell Configurations for the Simple

Mode of the PEEL20V8

Table 2. PEEL20V8 Device Mode/Macrocell Architecture Configuration Bits

Config.

Simple

Complex

Registered

Mode

MS0

Architecture Bits

MS1

Combinatorial

None

Combinatorial

Registered

Combinatorial

Active Low

Active High

None

Active Low

Active High

Active Low

Active High

Active Low

Active High

I/O Pin

Registered

I/O Pin

Function

Polarity

Feedback

3 - 27

PEEL

™

20V8

Simple mode also provides the option of configuring

an I/O pin as a dedicated input. In this case, the

output buffer is permanently disabled and the I/O

pin feedback is used to bring the input signal from

the pin into the logic array. This option is available

for all I/O pins except pins 18 and 19 (PLCC pins

21 and 23).

Complex Mode

In Complex mode, seven product terms feed the OR

array which can generate a purely combinatorial

function for the output pin. The programmable out-

put polarity selector provides active-high or active-

low logic, eliminating the need for external inverters.

Complex Mode

Active L ow Output

PRODUCT T ERM

Registered Mode

Active L ow R egistered Output

OE P IN

Registered Mode

Active High R egistered Outupt

OE P IN

CLK P IN

Registered Mode

Active L ow Combinatorial Output

Registered Mode

Active High Combinatorial Output

PRODUCT T ERM

Complex Mode

Active High Output

PRODUCT T ERM

Figure 5. Macrocell Configurations for the Regis-

tered Mode of the PEEL20V8

for input or bidirectional functions is available on all

I/O pins.

Figure 4. Macrocell Configurations for the Com-

plex Mode of the PEEL20V8

The output buffer is controlled by the eighth product

term, allowing the macrocell to be configured for

input, output or bidirectional functions. Feedback

into the array for input or bidirectional functions is

available on all pins except DIP pins 15 and 22

(PLCC pins 18 and 26). Figure 7 shows the logic

array of the PEEL20V8 configured in Complex

mode.

Registered Mode

Registered mode provides eight product terms to

the OR array for registered functions. The program-

mable output polarity selector provides active-high

or active-low logic, eliminating the need for external

inverters. (Note, however, that PEEL20V8 registers

power-up reset and so before the first clock arrives

the output at the pin will be low if the user has

selected active-high logic and high if the user has

selected active-low logic.) For registered functions,

the output buffer enable is controlled directly from

the /OE control pin. Feedback into the array comes

from the macrocell register. In Registered mode,

DIP input pins 1 and 13 (PLCC pins 2 and 16) are

permanently allocated as CLK and /OE, respec-

tively. Figure 8 shows the logic array of the

PEEL20V8 configured in Registered mode.

Registered mode also provides the option of config-

uring a macrocell for combinatorial operation, with

seven product terms feeding the OR function.

The programmable output polarity selector provides

active-high or active-low logic. The output buffer en-

able is controlled by the eighth product term, allow-

ing the macrocell to be configured for input, output

or bidirectional functions. Feedback into the array

3 - 28

Input and I/O Pin Pull-ups

The input and I/O pins on this device feature pull-up

circuitry. The pull-ups cause input and I/O pins to be

pulled high through nominally 100k ohms.

Design Security

The PEEL20V8 provides a special EEPROM secu-

rity bit that prevents unauthorized reading or copy-

ing of designs programmed into the device. The

security bit is set by the PLD programmer, either at

the conclusion of the programming cycle, or as a

separate step after the device has been pro-

grammed. Once the security bit has been set, it is

impossible to verify (read) or program the PEEL

until the entire device has first been erased with the

bulk-erase function.

Signature Word

The signature word feature allows a 64-bit code to

be programmed into the PEEL20V8. The code can-

not be read back after the security bit has been set.

The signature word can be used to identify the

pattern programmed into the device or to record the

design revision, etc.

PEEL

™

20V8

(2)

(3)

(27)

I/O

MACRO

CELL

(4)

(26)

I/O

MACRO

CELL

(5)

(25)

I/O

MACRO

CELL

(6)

(24)

I/O

MACRO

CELL

(7)

(23)

I/O

MACRO

CELL

(9)

(21)

I/O

MACRO

CELL

(10)

(20)

I/O

MACRO

CELL

(11)

(19)

I/O

MACRO

CELL

(12)

(13)

(18)

(17)

(16)

Figure 6. PEEL20V8 Logic Array - Simple Mode

(Pin numbers is for DIP package, PLCC pin numbers shown in parentheses.)

3 - 29

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

PEEL20V8J-15 Related Products

	PEEL20V8J-15	PEEL20V8P-15	PEEL20V8P-25	PEEL20V8J-25
Description	EE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28	EE PLD, 15ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	EE PLD, 25ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	EE PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
Maker	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）
Parts packaging code	QLCC	DIP	DIP	QLCC
package instruction	QCCJ,	DIP,	DIP,	QCCJ,
Contacts	28	24	24	28
Reach Compliance Code	unknown	unknown	unknown	unknown
maximum clock frequency	45.5 MHz	45.5 MHz	37 MHz	37 MHz
JESD-30 code	S-PQCC-J28	R-PDIP-T24	R-PDIP-T24	S-PQCC-J28
length	11.5062 mm	31.75 mm	31.75 mm	11.5062 mm
Dedicated input times	12	12	12	12
Number of I/O lines	8	8	8	8
Number of terminals	28	24	24	28
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	DIP	DIP	QCCJ
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE
Package form	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	15 ns	25 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	J BEND	THROUGH-HOLE	THROUGH-HOLE	J BEND
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	QUAD	DUAL	DUAL	QUAD
width	11.5062 mm	7.62 mm	7.62 mm	11.5062 mm

Recommended Resources

2Y-2Y connection two-speed motor switch control circuit

YSS-228 Karaoke Surround Sound Circuit

Multipurpose wireless remote control switch circuit

KA2309 (toy) radio remote control receiving control and regulating circuit

Microwave language anti-theft alarm

Computer motherboard circuit diagram 830_52

How to make a WinCE program developed with .net make a specified sound: The audio can be in any format....; chouxiaoya51 Embedded System

(nand) sd boot: [table=98%] [tr][td][color=#4f4f4f][font="][size=16px]256M是内存，[/size][/font][/color][color=#4f4f4f][font="][size=16px]256M[/size][/font][/color][color=#4f4f4f][font="][size=16px]是nand[/size][/font][/c...; 明远智睿Lan Linux and Android

EEWORLD University Hall----Live Replay: Introduction and Application of C2000? Built-in Programmable Logic Module CLB: Live replay: Introduction and application of C2000? built-in programmable logic module CLB : https://training.eeworld.com.cn/course/6088...; hi5 Integrated technical exchanges

Hanwang handwriting chip (handwriting module) HW006: I need help, where can I find HW006 handwriting module (how much is it)?...; liyz2169 Embedded System

RUWBUC2500X0T, ultra-high frequency filter, power supply interference consideration, EMC latest ultra-wideband filter: RUWBUC1600X0T, ultra-high frequency filter, power supply interference consideration, Ms. Peng 13713543851, Sanfeng Technology (Hong Kong) Co., Ltd. RF ultra-wideband filter, EMC high-frequency isolati...; samfongkaren Medical Electronics

[EEWorld invites you to play disassembly] —— A brief analysis of Baseus GaN charger 45W/65W: [i=s]This post was last edited by Beifang on 2021-8-4 11:46[/i]Continue from the previous post : https://bbs.eeworld.com.cn/thread-1174285-1-1.html 1. Baseus' GaN fast charging internal circuit has ma...; 北方 Power technology

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components