Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail:
admin@deiaz.com
DEI1084/1085
ARINC 429 ENHANCED
TRANSCEIVER
GENERAL DESCRIPTION
The DEI1084 is a CMOS ARINC 429 Transceiver IC. It
is pin compatible with the Holt HI-3584 and HI-8584
products.
The DEI2084 and DEI2085 are alternate package pin-out
version of 64L MLPQ package, which include TXSEL pin.
The enhancements relative to the DEI1016 transceiver
include: 32x32 bit FIFO for transmitter, 32x32 bit FIFO
for each receiver, a status register, label recognition
capability, bit timing feature and choice of scrambled or
unscrambled ARINC data output.
The DEI1085 version requires external serial 10KOhm
resistors on the receiver inputs. This simplifies the
implementation of external lightning protection networks.
The DEI1084 version has on-chip 10KOhm resistors and
do not require external resistors on the inputs.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
ARINC specification 429 compatible
3.3V/5.5V supply operation
Dual receiver and single transmitter interface
32nd transmit bit can be data or parity
Self test mode
Pin compatible with HI3584 & HI8584
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFO for transmitter and each receiver
Independent data rate selection for transmitter and
each receiver
Status register
Data scramble control
Package Options: 52L QFP, 52L CQFJ, & 64L
MLPQ
ORDERING INFORMATION
Part Number
DEI1084-QES-G
DEI1084-QMS-G
DEI1084-MES-G
DEI1084-UMS
DEI1085-QES-G
DEI1085-QMS-G
DEI1085-MES-G
DEI1085-UMS
DEI2084-MES-G
DEI2085-MES-G
DEI2084-MMS-G
DEI2085-MMS-G
Marking
DEI1084-QES
DEI1084-QMS
DEI1084-MES
DEI1084-UMS
DEI1085-QES
DEI1085-QMS
DEI1085-MES
DEI1085-UMS
DEI2084-MES
DEI2085-MES
DEI2084-MMS
DEI2085-MMS
Package
52L MQFP G
52L MQFP G
64L MLPQ G
52L CQFJ
52L MQFP G
52L MQFP G
64L MLPQ G
52L CQFJ
64L MLPQ G
64L MLPQ G
64L MLPQ G
64L MLPQ G
Burn In
No
No
No
No
No
No
No
No
No
No
No
No
10K Resistors
internal
internal
internal
internal
external
external
external
external
internal
external
internal
external
Temperature
-55 / +85 ºC
-55 / +125 ºC
-55 / +85 ºC
-55 / +125 ºC
-55 / +85 ºC
-55 / +125 ºC
-55 / +85 ºC
-55 / +125 ºC
-55 / +85 ºC
-55 / +85 ºC
-55 / +125 ºC
-55 / +125 ºC
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2011 Device Engineering Inc.
1 of 15
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PIN ASSIGNMENTS
©2011 Device Engineering Inc.
2 of 15
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FUNCTIONAL DESCRIPTION
ANALOG FRONT END (AFE) WITH LIGHTNING
PROTECTION. The AFE implements the analog detection
portion of the receiver circuit. The ARINC 429
characteristic describes RX detection levels as follows.
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5V to +13V
+2.5V to -2.5V
-6.5V to -13V
RECEIVER
The receiver signals (DI(A) and DI(B)) are differential,
bipolar, return-to-zero logic signals. The ARINC channels
can be connected directly to the receiver with no external
components.
Table 1: DEI1084 Pin Description
SIGNAL
VDD
RIN1A
RIN1B
RIN2A
RIN1B
/DR1
/FF1
/HF1
/DR2
/FF2
/HF2
SEL
/EN1
/EN2
BD[15:0]
GND
/NFD
/PL1
/PL2
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
POWER
INPUT
INPUT
INPUT
DESCRIPTION
Power Input: +3V or +5V .
ARINC receiver 1 positive input.
ARINC receiver 1 negative input.
ARINC receiver 2 positive input.
ARINC receiver 2 negative input.
Receiver 1 data flag ready.
Receiver 1 FIFO full.
Receiver 1 FIFO half full.
Receiver 2 data flag ready.
Receiver 2 FIFO full.
Receiver 2 FIFO half full.
Receiver data byte selection
(0 = BYTE 1) (1 = BYTE 2).
Data Bus control, enables receiver 1
data to output.
Data Bus control, enables receiver 2
data to output.
Data Bus.
Power and signal ground.
No frequency discrimination if low (pull
up)
Latch enable for byte 1 entered from
data bus to transmitter FIFO.
Latch enable for byte 2 entered from
data bus to transmitter FIFO.
follow /PL1.
TX/R
OUTPUT
Transmitter ready flag. Goes low when
ARINC word loaded into FIFO. Goes
high after transmission and FIFO empty.
/HFT
/FFT
429DO
/429DO
/TXSEL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Transmitter FIFO half full.
Transmitter FIFO full.
“ONES” data output from transmitter.
“ZEROS” data output from transmitter.
Transmitter Speed Select Status. Hi =
High speed,
Lo = Low speed. Inverted control word
“TXSEL”.
ENTX
/CWSTR
/RSR
CLK
TX CLK
/MR
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
Enable transmission.
Clock for control word register.
Read status register if SEL = 0, read
control register if SEL = 1 (pull up)
Master clock input.
Transmitter clock equal to master clock
(CLK), divided by either 10 or 80.
Master reset.
Must
The AFE detects the received ARINC line signal and
converts it into a stream of digital logic levels. It consists
of a pair of differential comparators per receiver capable of
±10V of common mode rejection. The AFE is powered by
an on chip 2.5V voltage regulator. This makes the part
capable of operating from a supply voltage ranging from
2.97V to 5.5V. The DEI1085 version parts bypass 10K
ohms of the input resistors, facilitating the use of 10K
external series resistors to provide lightning immunity
without impacting the input resistance specifications.
Lightning transient protection is provided at the receiver
input pins. The receiver input pins, in combination with
external 10K Ohm resistors, provide immunity to DO160
Level 3 Lightning Induced Transients. (These include the
600V peak damped sinusoid and 300V/150µs pulse). This
immunity is provided by the external 10K resistors
combined with the on-chip Zener diodes located within the
receiver input network. During a voltage transient, the
diodes shunt current to ground and drop most of the
transient voltage across the external resistors, thus
protecting the chip’s input pins.
When the internal resistor wire bond option is used, the
application must provide Transient Voltage Suppressor
(TVS) devices to limit transient voltage to ±50V.
16 BIT DATA BUS
A 16 Bit parallel bi-directional tri-state data bus provides
communication to the host.
SERIAL INTERFACE
The DEI1084 consists of two receive channels and one
transmit channel. Each receive channel operates
independently of each other and the transmitter. The
receive data is asynchronous to the transmitter data and
can also be at a different data rate than the transmitter.
TRANSMITTER
The transmitter clock is free running and in phase with the
transmitter data. The transmitter data (DO(A) and DO(B))
are TTL level signals. There are always at least 4 null bits
between data words. An external ARINC line driver is
required to interface the transmitter to the ARINC serial
data bus.
©2011 Device Engineering Inc.
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CONTROL REGISTER
A 16-bit control register is used to configure the device.
The control register bits CR0 – CR15 are loaded from
BD00 – BD15 when /CWSTR is pulsed low. The control
register contents are output on the data bus when SEL = 1
and /RSR is pulsed low. Each bit of the control register
has the following function:
Table 2: Control Register Bit definition
CR Bit
CR0
FUNCTION
Receiver 1
Data clock
Select
CR1
Label
Memory
Read/Write
CR2
Enable Label
Recognition
(Receiver 1)
CR3
Enable Label
Recognition
(Receiver 2)
CR4
CR5
Enable 32nd
bit as parity
Self Test
0
1
0
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
The 429DO and /429DO digital
outputs are internally connected to
the Rx logic inputs
1
CR6
Receiver 1
decoder
CR7
CR8
CR9
-
-
Receiver 2
decoder
CR10
CR11
CR12
-
-
Invert
Transmitter
parity
CR13
Transmitter
data clock
select
CR14
Receiver 2
Data clock
Select
CR15
Data format
0
1
Scramble ARINC data
Unscramble ARINC data
0
1
Data rate = HI = CLK/10
Data rate = LO = CLK/80
0
1
Data rate = HI = CLK/10
Data rate = LO = CLK/80
0
1
-
-
0
1
-
-
0
1
Normal operation
Receiver 1 decoder disabled
ARINC bits 9 and 10 must match
CR7 and CR8
If receiver 1 decoder is enabled, the
ARINC bit 9 must match this bit
If receiver 1 decoder is enabled, the
ARINC bit 10 must match this bit
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
If receiver 2 decoder is enabled, the
ARINC bit 9 must match this bit
If receiver 1 decoder is enabled, the
ARINC bit 10 must match this bit
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
1
0
1
Enable label recognition
Disable label recognition
Enable label recognition
0
0
1
Normal operation
Load 16 labels using /PL1,/PL2
Read 16 labels using /EN1, /EN2
Disable label recognition
STATE
0
1
DESCRIPTION
Data rate HI = CLK/10
Data rate LO= CLK/80
STATUS REGISTER
The device contains a 9-bit status register which can be
interrogated to determine the status of the ARINC
receivers, data FIFOs and transmitter. The contents of the
status register are output on BD0 - BD08 when the /RSR
pin is taken low and SEL = 0. Unused bits are output as
zeros. The following table defines the status register bits.
Table 3: Status Register Bit Definition
SR Bit
SR0
FUNCTION
Data ready
(Receiver 1)
STATE
0
1
DESCRIPTION
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid
data. Resets to zero when all data
has been read. /DR1 pin is the
inverse of this bit
SR1
FIFO
half full
(Receiver 1)
1
0
Receiver 1 FIFO holds less than
16 words
Receiver 1 FIFO holds at least 16
words. /HF1 pin is the inverse of
this bit
SR2
FIFO full
(Receiver 1)
0
1
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid
data loss, the FIFO must be read
within one ARINC word period.
/FF1 pin is the inverse of this bit.
SR3
Data ready
(Receiver 2)
0
1
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid
data. Resets to zero when all data
has been read. /DR2 pin is the
inverse of this bit
SR4
FIFO
half full
(Receiver 2)
1
0
Receiver 2 FIFO holds less than
16 words
Receiver 2 FIFO holds at least 16
words. /HF2 pin is the inverse of
this bit
SR5
FIFO full
(Receiver 2)
0
1
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid
data loss, the FIFO must be read
within one ARINC word period.
/FF2 pin is the inverse of this bit.
SR6
SR7
Transmitter
FIFO empty
Transmitter
FIFO full
SR8
Transmitter
FIFO
half full
1
0
1
0
1
0
Transmitter FIFO not empty
Transmitter FIFO empty
Transmitter FIFO not full
Transmitter FIFO full. /FFT pin
is the inverse of this bit
Transmitter FIFO contains less
than 16 words
Transmitter FIFO contains at least
16 words. /HFT pin is the inverse
of this bit
©2011 Device Engineering Inc.
4 of 15
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DATA FORMAT
Control register bit CR15 is used to control how individual
bits in the received or transmitted ARINC word are
mapped to the data bus during data read or write
operations. Table 4 describes this mapping:
Table 4: Parallel Data Bus Format, Scrambled & Not
Scrambled
DATA
BUS
BD00
BD01
BD02
BD03
BD04
BD05
BD06
BD07
BD08
BD09
BD10
BD11
BD12
BD13
BD14
BD15
ARINC BIT CR15 = 0
WORD1
WORD2
8 Label
14
7 Label
15
6 Label
16
5 Label
17
4 Label
18
3 Label
19
2 Label
20
1 Label
21
32 Parity
22
30
23
31
24
9 SDI
25
10 SDI
26
11
27
12
28
13
29
ARINC BIT CR15 = 1
WORD1
WORD2
1 Label
17
2 Label
18
3 Label
19
4 Label
20
5 Label
21
6 Label
22
7 Label
23
8 Label
24
9 SDI
25
10 SDI
26
11
27
12
28
13
29
14
30
15
31
16
32 Parity
If the /NFD pin is HI, the device accepts signals that meet
these specifications and rejects signals outside the
tolerances. The way this is achieved is described below:
/NFD=HI
/NFD=LO
LO Speed HI Speed
0.1KBPS
Data Bit Rate Min
10.4KBPS 83KBPS
Data Bit Rate Max
15.6KBPS 125KBPS 500KBPS
If /NFD pin is held low, frequency discrimination is
disabled and any data stream totaling 32 bits is accepted
even with gaps between bits. The protocol still requires a
word gap as defined in 4 above.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including
the parity bit. If the result is odd, then “0” will appear in
the 32nd bit.
RETRIEVING DATA
Once ARINC 32-bit word is recognized, the receiver logic
check for correct decoding and label matching prior to
loading the word into (or reject the word from) the 32 x 32
receiver FIFO. If CR2 or CR3 is/are ONE, then ARINC
words with have matching labels will be accepted into
Receiver FIFO. If CR6 or CR9 is/are ONE, then ARINC
words with matching decoder value (CR7, CR8 for RX1)
and (CR10, CR11 for RX2) will be accepted into Receiver
FIFO. The following table describes this operation:
Table 5: RX Data Filter Logic
CR2(3)
ARINC
word
matches
label
X
No
Yes
X
X
Yes
No
No
Yes
CR6(9)
ARINC word
bits 9&10
match CR7&8
(10&11)
X
X
X
No
Yes
No
Yes
No
Yes
FIFO
BIT TIMING
The ARINC 429 characteristic describes the RX
acceptance timing as follows.
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K to 14.4K BPS
BIT RATE
1.5 ± 0.5 µs
10 ± 5 µs
RISE TIME
1.5 ± 0.5 µs
10 ± 5 µs
FALL TIME
34.5 to 41.7 µs
PULSE WIDTH
5µs ± 5%
1. Key to the performance of timing checking logic is an
accurate 1 MHz clock source. Less than 0.1% error is
recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be
considered valid data. Additionally, for data bits, the One
or Zero in the upper bits of the sampling shift registers
must be followed by a Null in the lower bits within the
data bit time. For a Null in the word gap, three
consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the
minimum pulse width is guaranteed.
3. The Word Gap timer samples the Null shift register
every 10 input clocks (80 for low speed) after the last data
bit of a valid reception. If the Null is present, the Word
Gap counter is incremented. A count of 3 will enable the
next reception.
4. Each data bit must follow its predecessor by not less
than 8 samples and no more than 12 samples. In this
manner the bit rate is checked. With exactly 1 MHz clock
frequency, the acceptable data bit rates are as follows:
©2011 Device Engineering Inc.
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
Once a valid ARINC word is loaded into the FIFO, the
DATA READY FLAG will be turned on;
/DR1
or
/DR2
(or both) will go low. The data flag for a receiver will
remain low until all ARINC words are retrieved and the
Receiver FIFO is empty.
When data ready in Receiver FIFO, data can be retrieved
by activating (/EN1, SEL) or (/EN2, SEL) to output the
receiver data to the 16 bit parallel bus (see table 1).
Example to retrieve Receiver 1 data, first set (SEL = 0,
then /EN1 = 0) to place WORD1 on the 16-bit bus.
Release the 16-bit bus with (/EN1 = 1). Next set (SEL =1,
then /EN1 = 0) for WORD2. Last, release the 16-bit bus
with (/EN1 = 1). Use (/EN2) for Receiver 2 data retrieval.
Up to 32 ARINC words may be loaded into each receiver’s
FIFO. The /FF1 (/FF2) pin will go low when the receiver
1 (2) FIFO is full. Failure to retrieve data from a full FIFO
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