SN74HC73N-00 datasheet, PDF - EEWORLD Datasheet

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SN74HC73N-00: DescriptionHC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14; Categorylogic logic; File Size121KB，4 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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SN74HC73N-00 Overview

HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14

SN74HC73N-00 Parametric

Parameter Name	Attribute value
Maker	Texas Instruments
package instruction	DIP,
Reach Compliance Code	unknown
Other features	MASTER SLAVE OPERATION
series	HC/UH
JESD-30 code	R-PDIP-T14
length	19.305 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	32 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	25 MHz

SN74HC73N-00 Related Products

	SN74HC73N-00	SN74HC73D-00	SN74HC73N-10	SN74HC73DR-00
Description	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Reach Compliance Code	unknown	unknown	unknown	unknow
Other features	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION
series	HC/UH	HC/UH	HC/UH	HC/UH
JESD-30 code	R-PDIP-T14	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14
length	19.305 mm	8.65 mm	19.305 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2	2	2
Number of functions	2	2	2	2
Number of terminals	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SOP	DIP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE
propagation delay (tpd)	32 ns	32 ns	32 ns	32 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	1.75 mm	5.08 mm	1.75 mm
Maximum supply voltage (Vsup)	6 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	THROUGH-HOLE	GULL WING	THROUGH-HOLE	GULL WING
Terminal pitch	2.54 mm	1.27 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	7.62 mm	3.9 mm	7.62 mm	3.9 mm
minfmax	25 MHz	25 MHz	25 MHz	25 MHz
package instruction	DIP,	-	DIP,	SOP,

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