IS25LD040-JBLE datasheet, PDF - EEWORLD Datasheet

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IS25LD040-JBLE: DescriptionFlash, 512KX8, PDSO8, 0.208 INCH, LEAD FREE, SOIC-8; Categorystorage storage; File Size643KB，34 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS25LD040-JBLE Overview

Flash, 512KX8, PDSO8, 0.208 INCH, LEAD FREE, SOIC-8

IS25LD040-JBLE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
package instruction	SOP, SOP8,.3
Reach Compliance Code	compliant
Factory Lead Time	14 weeks
Maximum clock frequency (fCLK)	100 MHz
Data retention time - minimum	20
Durability	200000 Write/Erase Cycles
JESD-30 code	S-PDSO-G8
length	5.28 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	8
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.3
Package shape	SQUARE
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
power supply	2.5/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	2.16 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
type	NOR TYPE
width	5.28 mm
write protect	HARDWARE/SOFTWARE

IS25LD040-JBLE Preview

IS25LD040

4 Mbit Single Operating Voltage Serial Flash Memory

With 100 MHz Dual-Output SPI Bus Interface

FEATURES

•

Single Power Supply Operation

- Low voltage range: 2.30 V - 3.60 V

• Memory Organization

- IS25LD040: 512K x 8 (4 Mbit)

•

Cost Effective Sector/Block Architecture

- 4Mb : Uniform 4KByte sectors / Eight uniform

64KByte blocks

• Low standby current 1uA (Typ)

•

Serial Peripheral Interface (SPI) Compatible

- Supports single- or dual-output

- Supports SPI Modes 0 and 3

- Maximum 33 MHz clock rate for normal read

- Maximum 100 MHz clock rate for fast read

•

Page Program (up to 256 Bytes) Operation

- Typical 2 ms per page program

•

Sector, Block or Chip Erase Operation

- Maximum 10ms sector, block or chip erase

•

Low Power Consumption

- Typical 10 mA active read current

- Typical 15 mA program/erase current

•

Hardware Write Protection

- Protect and unprotect the device from write

operation by Write Protect (WP#) Pin

•

Software Write Protection

The Block Protect (BP2, BP1, BP0) bits allow

partial or entire memory to be configured as read-

only

•

High Product Endurance

- Guaranteed 200,000 program/erase cycles per

single sector

- Minimum 20 years data retention

•

Industrial Standard Pin-out and Package

- 8-pin 150mil SOIC

- 8-pin 208mil SOIC

- 8-pin WSON

- 8-pin 150mil VVSOP

- KGD

- Lead-free (Pb-free), package

GENERAL DESCRIPTION

The IS25LD040 are 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output.

The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the

fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from

2.30 Volt to 3.60 Volt, to perform read, erase and program operations. The devices can be programmed in

standard EPROM programmers.

The IS25LD040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial

Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command

codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz.

The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in

one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.

The IS25LD040 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in

8-pin 208mil SOIC, 8-pin SOIC 150mil, 8-pin VVSOP 150mil, and 8-pin WSON . The devices operate at wide

temperatures between -40°C to +105°C.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

07/31/2013

IS25LD040

CONNECTION DIAGRAMS

CE#

Vcc

HOLD#

CE#

8 Vcc

7 HOLD#

6 SCK

5 SIO

WP# 3

WP#

SCK

GND 4

GND

SIO

8-Pin SOIC/VVSOP

8-Pin WSON

PIN DESCRIPTIONS

SYMBOL

CE#

TYPE

INPUT

DESCRIPTION

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (Sl), and the

serial output pin (SO) will remain in a high impedance state.

Serial Data Clock

Serial Data Input/Output

Serial Data Output

Ground

Device Power Supply

Write Protect: A hardware program/erase protection for all or part of a

memory array. When the WP# pin is low, memory array write-protection depends

on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is

high, the devices are not write-protected.

Hold: Pause serial communication by the master device without resetting

the serial sequence.

SCK

SIO

GND

Vcc

WP#

INPUT

INPUT/OUTPUT

OUTPUT

INPUT

HOLD#

INPUT

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

07/31/2013

IS25LD040

BLOCK DIAGRAM

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

07/31/2013

IS25LD040

SPI MODES DESCRIPTION

Multiple IS25LD040 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e.

microcontroller, as shown in Figure 1. The devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer

to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output

data is available from the falling edge of SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDIO

SPI Interface with

(0,0) or (1,1)

SDI

SCK

SPI Master

(i.e. Microcontroller)

CS3

CS2

CS1

CE#

SIO

SCK

SIO

SCK

SIO

SPI Memory

Device

SPI Memory

Device

SPI Memory

Devic

CE#

WP#

HOLD#

WP#

HOLD#

CE#

WP#

HOLD#

Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

appropriate.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

07/31/2013

IS25LD040

Figure 2. SPI Modes Supported

SCK

Mode 0 (0, 0)

SCK

Mode 3 (1, 1)

SIO

Input mode

MSb

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

07/31/2013

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