EEWORLDEEWORLDEEWORLD

Part Number

Search

LP21-18-FREQ2-20F3CC

Description
Parallel - 3Rd Overtone Quartz Crystal, 32MHz Min, 50MHz Max, ROHS COMPLIANT PACKAGE-2
CategoryPassive components    Crystal/resonator   
File Size92KB,6 Pages
ManufacturerPletronics
Environmental Compliance  
Download Datasheet Parametric View All

LP21-18-FREQ2-20F3CC Overview

Parallel - 3Rd Overtone Quartz Crystal, 32MHz Min, 50MHz Max, ROHS COMPLIANT PACKAGE-2

LP21-18-FREQ2-20F3CC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPletronics
package instructionROHS COMPLIANT PACKAGE-2
Reach Compliance Codecompliant
Other featuresAT-CUT CRYSTAL; BULK
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - 3RD OVERTONE
Drive level1000 µW
frequency stability0.002%
frequency tolerance20 ppm
JESD-609 codee3
load capacitance18 pF
Manufacturer's serial numberLP21
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency50 MHz
Minimum operating frequency32 MHz
Maximum operating temperature50 °C
Minimum operating temperature
physical sizeL10.8XB4.47XH2.1 (mm)/L0.425XB0.176XH0.083 (inch)
Series resistance80 Ω
surface mountNO
Terminal surfaceMatte Tin (Sn)
LP21 / LP24 / LP49 Series
Low Profile Crystal
February 2010
• The Pletronics’ LP49 Series is a low profile
thru-hole crystal
• Bulk packaging
• 3 MHz to 70 MHz
• HC-49/US
• AT Cut Crystal
LP21 0.082 (2.10mm) high
LP24 0.100 (2.50mm) high
LP49 0.140 (3.56mm) high
Pletronics Inc. certifies this device is in accordance with the
RoHS (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead (<1000 ppm), Mercury, PBB’s, PBDE’s
Weight of the Device: 0.62 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e1, e2 or e3
Electrical Specification:
Item
Frequency Range
Calibration Frequency Tolerance
Frequency Stability over OTR
Equivalent Series Resistance
(ESR)
Min
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Drive Level
Shunt Capacitance
Aging per year
Specified Temperature Range
Storage Temperature Range
(C0)
-
-
-5
-40
-55
Max
70
-
-
200
150
120
100
80
70
60
50
40
35
100
80
60
1
7
+5
+85
+125
Unit
MHz
ppm
ppm
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
mW
pF
ppm
o
o
Condition
AT cut
at +25
o
C + 3
o
C
_
see table on page 3 for
available options
LP49
LP49/LP24
LP49/LP24
LP49/LP24
LP49/LP24
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
3
rd
Overtone
Fundamental
3 MHz to 4 MHz
4 MHz to 5 MHz
5 MHz to 6 MHz
6 MHz to 7 MHz
7 MHz to 9 MHz
9 MHz to 10 MHz
10 MHz to 13 MHz
13 MHz to 15 MHz
15 MHz to 27 MHz
27 MHz to 30 MHz
27 MHz to 32 MHz
32 MHz to 50 MHz
50 MHz to 70 MHz
use 10 µW for testing
Pad to Pad capacitance
at +25
o
C + 3
o
C
_
see table on page 3 for available options
C
C
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics limited warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2010, Pletronics Inc.
Please help me see the following OTDR data
Name Distance Welding Point Attenuation Factor odf1-1 0.97km 0.21 0.43db/km odf1-1 1.26km 3.13 0.067db/km odf3-19 0.23km -0.089 1.412db/km odf3-19 0.95 km 0 .451 0.318db/km odf3-15 0.16 km 0.387 -1.79...
youyouha RF/Wirelessly
Help with 485 enable analysis
Please help, what is the function of adding this circuit to the 485 enable? ? ? If RXD plus a NOT gate is used to control the enable, what is the difference between the two? ? ? ?...
Simonbinbin Making friends through disassembly
Does anyone have the IO interface definition of the S3C6410 development board? The project requires LVCMOS 3.3V IO
Does anyone have the IO interface definition of the S3C6410 development board? The project requires LVCMOS 3.3V IO. I looked at the one from Feiling and it seems to be TTL level. Is there any LVCMOS? ...
yanbing_90 Embedded System
The component list of the 2017 National College Student Electronic Design Competition has been officially announced. Are you ready?
[align=left][size=4][color=#0000ff]Yesterday, the list of instruments and main components for the 2017 National Undergraduate Electronic Design Competition was officially announced in advance. How are...
eric_wang Electronics Design Contest
An engineer's experience in FPGA project development
1. Cooperate with others. Take our hardware engineers as an example. When testing, software cooperation is generally required. A task that is extremely complex for hardware may be just a few lines of ...
liumnqti FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 979  1523  2834  367  531  20  31  58  8  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号