TRU050-TCLNB-35M3280000 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> TRU050-TCLNB-35M3280000

TRU050-TCLNB-35M3280000: DescriptionPhase Locked Loop, CDIP16, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size172KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

TRU050-TCLNB-35M3280000 Overview

Phase Locked Loop, CDIP16, SMD-16

TRU050-TCLNB-35M3280000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
Parts packaging code	DIP
package instruction	DIP,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDIP-T16
JESD-609 code	e4
length	20.32 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.62 mm

Preview

Download Datasheet

View All

TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85°C Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-based

PLL integrated circuit. It includes a digital phase

detector, op-amp, VCXO and additional integrated

functions for use in digital synchronization

applications. Loop filter software is available as well

SPICE models for circuit simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Page 1 of 14

Rev: 26Aug2008

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.

DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about

a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN

and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by

more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a

block diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does

not have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be

centered in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3

volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ

signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant

ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications

such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so

under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will not vary

signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary

according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev: 26Aug2008

Recommended Resources

Coal stove door automatic opening remote control circuit

STK4182 II power amplifier circuit diagram

Circuit diagram of separately excited switching stabilized power supply using single-junction transistor as pulse generator

Positive and negative symmetrical power conversion circuit diagram

555 simple water level monitoring circuit

Receiving circuit composed of TDA7021T

How to configure TIM1_CH1 for output comparison: How to configure TIM1_CH1 for output comparison? Why does the example program modified directly by OCToggle in V3.2.0 not work,but the one modified by TIM2_CH1 works?...; GGRR stm32/stm8

Analysis of causes of electrical fast transient (EFT) failure and sharing of rectification experience: [size=4][b]1. Reasons for failure[/b] The electrical fast pulse test is of typical significance for testing the immunity of equipment. Since the rising edge of the electrical fast pulse test waveform ...; 木犯001号 Power technology

[ST Motor Evaluation] Task Initialization - Environment Construction: [b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]stp111[/size]. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and ind...; stp111 stm32/stm8

ARM programming mode and some conceptual understanding: [backcolor=white][size=4][color=#000000]1. ARM programming mode and 7 working modes[/color][/size][/backcolor] [backcolor=white][size=4][color=#000000] [/color][/size][/backcolor] [backcolor=white][si...; Aguilera DSP and ARM Processors

Please tell me how to add an interrupt service routine in PXA270!!!: I need to add an interrupt in BSP, the interrupt pin is GPIO36. BSP is under WINCE42, which is the kind of static interrupt application. My steps: 1. In OALINTR.H, I added [b]#define SYSINTR_WIFI (SYS...; wyh121w Embedded System

Can this io interrupt be implemented? It has been compiled without errors.: char char_gen[10]={0X7D,0X60,0X3E,0X7A,0X63,0X5B,0x5F,0X70,0X7F,0X7B};unsigned int i,j,a,b,c,d; #include"msp430x41x2.h"#define MCLK_C ((double)1000000) #define delay_s(x) __delay_cycles((long)(MCLK_C*...; qwe2549325 Microcontroller MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components