K3P7V(U)2000A-SC
64M-Bit (4Mx16 /2Mx32) CMOS MASK ROM
FEATURES
•
Switchable organization
4,194,304 x 16(word mode)
2,097,152 x 32(double word mode)
•
Fast access time
Random Access/Page Access
3.3V Operation : 100/30ns(Max.)
3.0V Operation : 120/40ns(Max.)
4 double Words / 8 Words page access
•
Supply voltage : single +3.0V/ single +3.3V
•
Current consumption
Operating : 60mA(Max.)
Standby : 30µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. K3P7V(U)2000A-SC : 70-SSOP-500
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P7V(U)2000A-SC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 4,194,304 x 16 bit(word mode) or as
2,097,152 x 32 bit(double word mode) depending on WORD
voltage level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 double words (or 8 words) of data to read fast in the
same page, CE and A
2
~ A
20
should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P7V(U)2000A-SC is packaged in a 70-SSOP.
FUNCTIONAL BLOCK DIAGRAM
A
20
.
.
.
.
.
.
.
.
A
2
A
0
, A
1
A
-1
CE
OE
WORD
Pin Name
A
0
- A
1
A
2
- A
20
Q
0
- Q
30
Q
31
/A
-1
WORD
CE
OE
V
CC
V
SS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 31(Double word mode)/
LSB Address(Word mode)
Double word/Word mode selection
Chip Enable
Output Enable
Power
Ground
No Connection
CONTROL
LOGIC
Q
0
/Q
16
Q
15
/Q
31
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(2,097,152x32/
4,194,304x16)
PIN CONFIGURATION
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
Q
0
Q
16
Q
1
Q
17
V
SS
V
CC
Q
2
Q
18
Q
3
Q
19
Q
4
Q
20
Q
5
Q
21
V
SS
V
CC
Q
6
Q
22
Q
7
Q
23
V
SS
A
6
A
7
A
8
A
9
A
10
A
11
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
N.C
N.C
A
20
WORD
OE
CE
V
SS
Q
31
/A
-1
Q
15
Q
30
Q
14
V
SS
V
CC
Q
29
Q
13
Q
28
Q
12
Q
27
Q
11
Q
26
Q
10
V
SS
V
CC
Q
25
Q
9
Q
24
Q
8
V
CC
A
19
A
18
A
17
A
16
A
15
A
14
A
13
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
SSOP
K3P7V(U)2000A-SC
K3P7V(U)2000A-SC
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Symbol
V
IN
T
BIAS
T
STG
Rating
CMOS MASK ROM
Unit
V
°C
°C
-0.3 to +4.5
-10 to +85
-55 to +150
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70°C)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400µA
I
OL
=2.1mA
Test Conditions
CE=OE=V
IL
,
all outputs open
V
CC
=3.3V±0.3V
V
CC
=3.0V±0.3V
Min
-
Max
60
50
500
30
-
-
2.0
-0.3
2.4
-
10
10
V
CC
+0.3
0.6
-
0.4
Unit
mA
mA
µA
µA
µA
µA
V
V
V
V
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
L
OE
X
H
L
WORD
X
X
H
L
Q
31
/A
-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operating
Data
High-Z
High-Z
Q
0
~Q
31
:Dout
Q
0
~Q
15
: Dout
Q
16
~Q
30
: Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
12
12
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
K3P7V(U)2000A-SC
CMOS MASK ROM
AC CHARACTERISTICS
(T
A
=0°C to 70°C, V
CC
=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and C
L
=100pF
READ CYCLE
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to Output High-Z
Output Hold from Address Change
NOTE
: Page Address is determined as below.
Double Word mode (WORD=V
IH
) : A
0
, A
1
Word mode (WORD=V
IL
) : A
-1
, A
0
, A
1
Symbol
t
RC
t
ACE
t
AA
t
PA
t
OE
t
DF
t
OH
V
CC
=3.3V±0.3V
Min
100
100
100
30
30
20
0
Max
V
CC
=3.0V±0.3V
Min
120
120
120
40
40
20
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
K3P7V(U)2000A-SC
TIMING DIAGRAM
READ
ADD
A
0
~A
20
A
-1(*1)
t
ACE
CE
t
OE
OE
t
OH
D
OUT
D
0
~D
15
D
16
~D
31(*2)
VALID DATA
t
AA
CMOS MASK ROM
ADD1
t
RC
ADD2
t
DF(*3)
VALID DATA
PAGE READ
≈
CE
t
DF(*3)
OE
ADD
A
0,
A
1
A
-1(*1)
t
AA
D
OUT
D
0
~D
15
D
16
~D
31(*2)
1 st
t
PA
VALID DATA
2 nd
3 rd
≈
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1. Word Mode only. A
-1
is Least Significant Bit Address.(WORD = V
IL
)
*2. Double Word Mode only.(WORD = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
≈
≈
≈
≈
ADD
A
2
~A
20
≈
≈
K3P7V(U)2000A-SC
PACKAGE DIMENSIONS
70-SSOP-500
#70
#36
CMOS MASK ROM
(Unit : mm/inch)
0~8°
15.90±
0.30
0.626±
0.012
12.70±
0.10
0.500±
0.004
15.24
0.600
+0.10
#1
#35
0.15
-0.05
0.006
+0.004
-0.002
2.70±
0.10
0.106±
0.004
3.10
0.122 MAX
0.10 MAX
0.004 MAX
0.80±
0.20
0.031±
0.008
28.97 MAX
1.141
28.57±
0.10
1.125±
0.004
(
0.685
)
0.027
0.30
+0.10
-0.05
+0.004
0.012
-0.002
0.80
0.031
0.05
MIN
0.002
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